Document
UMER
350 BISHOP'S WAY
BROOKFIELD, WI. S3005
414 I 784·6641
HD64180 8·BIT HIGH INTEGRATION CMOS MICROPROCESSOR
DATA BOOK
-ADVANCE INFORMATION-
~HITACHI#un
AD-E0039
This advance data has been preliminarily prepared based on manuscript translated in Japan. Use this information with caution, therefore, as the accuracy of the copy cannot be guaranteed. A revised, U.S. edition of this technical data is currently in preparation, and may be ordered by returning the Business Reply Card at the back of this publication.
When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2. All rights reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part ofthis manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result from accidents or any other reasons during operation of his unit according to this manual.
4. This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof.
Printed in U.S.A.
Published: February 1985
TABLE OF CONTENTS
1. HD64180 OVERViEW................................................. 3 1.1 Block Diagram, Pin Assignment and Packaging .................... , 3 1.2 CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 1.3 1/0 Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
2. HD64180 HARDWARE ARCHITECTURE................................ 7
2.1 Signal Description. . . . . .... . . . . . . . . . . . . . .. .. . . . .. . .. . . . . . . . . . . . . . . 7 2.2 CPU Bus Timing ................................................ 12 2.3 WAIT State Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 2.4 HALT, SLEEP and Low Power Operation .......................... 21 2.5 1/0 and Control Registers ....................................... , 24 2.6 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27 2.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 34 2.8 Dynamic RAM Refresh Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 48 2.9 DMA Controller (DMAC) ....................................... 51 2.10 Asynchronous Serial Communication Interface (ASCI) ....... . . . . . .. 64 2.11 Clocked Serial 1/0 Port (CSIIO) ................................... 74 2.12 Programmable Reload Timer (PRT) ............................... 80 2.13 6800 Type Bus Interface.. . . . . . . . .. .. .. . . . .. . . .. . . . . . .. . .. . . . . . . .. 85 2.14 On-chip Clock Generator ......................................... 88
3. HD64180 SOFTWARE ARCHITECTURE ................................ 91 3.1 Instruction Set. ................................................. , 91 3.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 92 3.3 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95
4. HD64180 ELECTRICAL CHARACTERISTICS .... . . . . . . . . . . . . . . . . . . . . . . .. 99
APPENDIX
A Instruction Set. .................................................. 113 B Instruction Summary in Alphabetical Order .......... " ............. 144 COp-code Map .................................................... 154 D Bus and Control Signal Condition in each Machine Cycle ............ 158 E-1 Request Acceptances in Each Operating Mode ...................... 177 E-2 Request Priority ................................................. 178 F Status Signals.................................................... 179 G Internal 110 Registers ............................................ 180
Figure No.
1.1.1 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.4.1 2.4.2 2.5.1 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.7.1 2.7.2 (a) 2.7.2 (b) 2.7.3 2.7.4 2.7.5
2.7.6 2.7.7 2.7.8 2.7.9 2.7.10 2.7.11 2.8.1 2.9.1 2.9.2
Figures
Description
Block Diagram Op-code Fetch Timing Op-code Fetch Timing (with wait state) Memory Read/Write Timing (without wait state) Memory Read/Write Timing (with wait state) I/O Read/Write Timing
LD (IX+ d), g Instruction Timing
RESET Timing Bus Exchange Timing (1) Bus Exchange Timing (2) HALT Timing SLEEP Timing On-chip I/O Address Relocation Logical Address Mapping Examples Logical - Physical Memory Mapping Example MMU Block Diagram I/O Address Translation Logical Memory Organization Logical Space Configuration (Example) Physical Address Generation Interrupt Sources TRAP - 2nd Op-code Undefined TRAP - 3rd Op-code Undefined NMI Sequence NMI Timing INTO Mode 0 Timing (RST Instruction on the Data Bus) INTO Mode 1 Interrupt Sequence INTO Mode 1 Timing INTO Mode 2 Vector Acquisition INTO Mode 2 Timing INT.