Document
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface
Features
■ Memories
– 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices
– 1K to 2K RAM – HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C ■ Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
– PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow ■ Interrupt Management
– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – Top Level Interrupt (TLI) pin on 64-pin devices – 15/9 external interrupt lines (on 4 vectors) ■ Up to 48 I/O Ports
– 48/32/24 multifunctional bidirectional I/O lines – 34/22/17 alternate function lines – 16/12/10 high sink outputs ■ 5 Timers
– Main Clock Controller with: Real time base, Beep and Clock-out capabilities
– Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one timer, PWM and pulse generator modes
LQFP64 14 x 14
LQFP32 7x7
LQFP64 10 x 10
LQFP44 10 x 10
– 8-bit PWM Auto-reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
■ 3 Communications Interfaces
– SPI synchronous serial interface – SCI asynchronous serial interface – I2C multimaster interface ■ 1 Analog peripheral (low current coupling)
– 10-bit ADC with up to 16 robust input ports ■ Instruction Set
– 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction ■ Development Tools
– Full hardware/software development package – In-Circuit Testing capability
Table 1. Device Summary
Features
Program memory bytes RAM (stack) - bytes Operating Voltage Temp. Range Package
ST72321BAR9/ ST72321BR9/ ST72321BJ9
ST72321BAR7/ ST72321BR7/ ST72321BAR6/ ST72321BR6/
ST72321BJ7
ST72321BJ6/ST72321BK6
FLASH/ROM 60K
FLASH/ROM 48K
FLASH/ROM 32K
2048 (256)
1536 (256)
1024 (256)
3.8V to 5.5V
up to -40°C to +125°C
LQFP64 10x10 (AR),LQFP64 14x14 (R), LQFP44 10x10 (J), LQFP32 7x7 (K)
October 2008
Rev 5
1/187
1
Table of Contents
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..