DatasheetsPDF.com

NT5CB64M16FP Dataheets PDF



Part Number NT5CB64M16FP
Manufacturers Nanya
Logo Nanya
Description 1Gb SDRAM
Datasheet NT5CB64M16FP DatasheetNT5CB64M16FP Datasheet (PDF)

DDR3(L) 1Gb SDRAM NT5CB(C)128M8FN / NT5CB(C)64M16FP Nanya Technology Corp. NT5CB(C)128M8FN / NT5CB(C)64M16FP Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode  Si.

  NT5CB64M16FP   NT5CB64M16FP



Document
DDR3(L) 1Gb SDRAM NT5CB(C)128M8FN / NT5CB(C)64M16FP Nanya Technology Corp. NT5CB(C)128M8FN / NT5CB(C)64M16FP Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 7 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)  Speed Grade (CL-TRCD-TRP) 2,3 - 2133 Mbps / 14-14-14 - 1866 Mbps / 13-13-13 - 1600 Mbps / 10-10-10,11-11-11 Options  Temperature Range (Tc) 5 - Commercial Grade = 0℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ Programmable Functions  CAS Latency (5/6/7/8/9/10/11/12/13/14)  CAS Write Latency (5/6/7/8/9/10)  Additive Latency (0/CL-1/CL-2)  Write Recovery Time (5/6/7/8/10/12/14/16)  Burst Type (Sequential/Interleaved)  Burst Length (BL8/BC4/BC4 or 8 on the fly)  Self RefreshTemperature Range(Normal/Extended)  Output Driver Impedance (34/40)  On-Die Termination of Rtt_Nom(20/30/40/60/120)  On-Die Termination of Rtt_WR(60/120)  Precharge Power Down (slow/fast) Packages / Density Information Lead-free RoHS compliance and Halogen-free 1Gb (Org. / Package) Length x Width Ball pitch (mm) (mm) 128Mbx8 78-ball TFBGA 8.00 x 10.50 0.80 64Mbx16 96-ball TFBGA 9.00 x 13.00 0.80 Density and Addressing Organization Bank Address Auto precharge BL switch on the fly Row Address Column Address Page Size tREFI(us) 5 tRFC(ns) 6 128Mb x 8 64Mb x 16 BA0 – BA2 BA0 – BA2 A10 / AP A12 /  A10 / AP A12 /  A0 – A13 A0 – A9 A0 – A12 A0 – A9 1KB 2KB Tc<=85℃:7.8, Tc>85℃:3.9 110ns NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 NOTE 6 NOTE 7 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand. The timing specification of high speed bin is backward compatible with low speed bin. Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS). SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled. Violating tRFC specification will induce malfunction. Only Support prime DQ’s feedback for each byte lane. Please contact with NTC for the feedback.


NT5CB128M8FN NT5CB64M16FP NT5CC128M8FN


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)