Document
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Feature
1.5V ± 0.075V (JEDEC Standard Power Supply) 8 Internal memory banks (BA0- BA2) Differential clock input (CK, ) Programmable Latency: 5, 6, 7, 8, 9 Programmable Additive Latency: 0, CL-1, CL-2 Programmable Sequential / Interleave Burst Type Programmable Burst Length: 4, 8 8 bit prefetch architecture Output Driver Impedance Control
Write Leveling OCD Calibration Dynamic ODT (Rtt_Nom & Rtt_WR) Auto Self-Refresh Self-Refresh Temperature Partial Array Self-Refresh RoHS Compliance Packages:
78-Ball BGA for x4 & x8 components 96-Ball BGA for x16 components
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.75V power supply and are available in BGA packages.
REV 1.2
01 / 2009
1
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Pin Configuration – 78 balls BGA Package (x4)
< TOP View>
See the balls through the package
1 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS
2 VDD VSSQ DQ2 NC VDDQ VSS VDD BA0
A3 A5 A7
3 NC DQ0 DQS NC BA2 A0 A2 A9 A13
x4 7
A NC B DM C DQ1 D VDD E NC F CK G H A10/AP J NC K A12/ L A1 M A11 N NC
8 VSS VSSQ DQ3 VSS NC VSS VDD ZQ VERFCA BA1
A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
REV 1.2
01 / 2009
2
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Pin Configuration – 78 balls BGA Package (x8)
< TOP View>
See the balls through the package
1 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS
2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD BA0
A3 A5 A7
3 NC DQ0 DQS DQ4 BA2 A0 A2 A9 A13
x8 7
A NU/ B DM/TDQS C DQ1 D VDD E DQ7 F CK G H A10/AP J NC K A12/ L A1 M A11 N NC
8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VERFCA BA1
A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
REV 1.2
01 / 2009
3
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Pin Configuration – 96 balls BGA Package (x16)
1 VDDQ VSSQ VDDQ VSSQ
VSS VDDQ VSSQ VREFDQ
NC ODT NC VSS VDD VSS VDD VSS
< TOP View>
See the balls through the package
2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VSS VDD
BA0 A3 A5 A7
3 DQU7
VSS DQU1 DMU DQL0 DQSL DQL4
BA2 A0 A2 A9 NC
x 16 A
7 DQU4
B
C DQSU
D DQU0
E DML
F DQL1
G VDD
H DQL7
J CK K
L A10/AP
M NC N A12 P A1
R A11 T NC
8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5
VSS VDD ZQ VREFCA BA1 A4 A6 A8
9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS
REV 1.2
01 / 2009
4
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
Input / Output Functional Description
Symbol
Type
Function
CK,
Input
Clock: CK and are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of .
CKE
, , DM, (DMU, DML)
BA0 - BA2
A0 – A13
A12 / BC# DQ
DQU, DQL DQS, () DQSL, (), DQSU,()
Input Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when is registered high. provides for external rank selection on systems with multiple memory ranks. is considered part of the command code.
Input
Command Inputs: , and (along with ) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
Input
sampled HIGH coincident with that input data during .