Document
FUJITSU SEMICONDUCTOR DATA SHEET
DS709-00003-0v01-E
32-bit ARMTM CortexTM-M4F based Microcontroller
MB9B360R Series
MB9BF366M/N/R, MB9BF367M/N/R, MB9BF368M/N/R
DESCRIPTION
The MB9B360R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost.
These series are based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE4 product categories in "FM4 Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.6
MB9B360R Series
FEATURES
32-bit ARM Cortex-M4F Core ・Processor version: r2p1 ・Up to 160 MHz Frequency Operation ・FPU built-in ・Support DSP instruction ・Memory Protection Unit (MPU): improves the reliability of an embedded system ・Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels ・24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories [Flash memory]
These series are based on two independent on-chip Flash memories.
・MainFlash memory ・ Up to 1024 Kbytes ・ Built-in Flash Accelerator System with 16 Kbytes trace buffer memory ・ The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. ・ Security function for code protection
・WorkFlash memory ・ 32 Kbytes ・ Read cycle: ・6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz ・4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz ・2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz ・0wait-cycle: the operation frequency up to 40MHz ・ Security function is shared with code protection
[SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.
・SRAM0: Up to 64 Kbytes ・SRAM1: Up to 32 Kbytes ・SRAM2: Up to 32 Kbytes
External Bus Interface ・Supports SRAM, NOR, NAND Flash and SDRAM device ・Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) ・8/16-bit Data width ・Up to 25-bit Address bit ・Supports Address/Data multiplex ・Supports external RDY function ・Supports scramble function ・Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. ・Possible to set two kinds of the scramble key Note: It is necessary to prepare the dedicated software library to use the scramble function.
2 DS709-00003-0v01-E
MB9B360R Series
USB Interfa.