ICS93732

Integrated Circuit Systems, Inc. ICS9373 2 Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: Low skew, low jitter PLL clock driver Max frequency supported = 266MHz (DDR 533) I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3.3V tolerant CLK_INT input Switching Characteristics: CYCLE - CYCLE jitter (66MHz): <120ps CYCLE - CYCLE jitter (>100MHz): <65ps CYCLE - CYCLE jitter (>200MHz): <75ps OUTPUT - OUTPUT skew: <100ps DUTY CYCLE: 49.5% - 50.5% Pin Configuration DDRC0 1 DDRT0 2 VDD 3 DDRT1 4 DDRC1 5 GND 6 SCLK 7 CLK_INT 8 N/C 9 VDDA 10 GND 11 VDD 12 DDRT2 13 DDRC2 14 ICS93732 28 GND 27 DDRC5 26 DDRT5 25 DDRC4 24 DDRT4 23 VDD 22 SDATA 21 N/C 20 FB_INT 19 FB_OUT 18 N/C 17 DDRT3 16 DDRC3 15 GND 28-Pin 209mil SSOP 28-Pin 173mil TSSOP Block Diagram SCLK SDATA Control Logic FB_INT CLK_INT PLL FB_OUTT DDRT0 DDRC0 DDRT1 DDRC1 DDRT2 DDRC2 DDRT3 DDRC3 DDRT4 DDRC4 DDRT5 DDRC5 Functionality INPUTS OUTPUTS PLL State AVDD CLK_INT CLKT CLKC FB_OUTT 2.5V (nom) L LH L on 2.5V (nom) H HL H on 0578H—02/19/04 ICS9373 2 Pin Descriptions PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PIN NAME DDRC0 DDRT0 VDD DDRT1 DDRC1 GND SCLK CLK_INT N/C VDDA GND VDD DDRT2 DDRC2 GND DDRC3 DDRT3 N/C FB_OUT 20 FB_INT 21 N/C 22 SDATA 23 VDD 24 DDRT4 25 DDRC4 26 DDRT5 27 DDRC5 28 GND PIN TYPE DESCRIPTION ...