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MPC875 Dataheets PDF



Part Number MPC875
Manufacturers Freescale Semiconductor
Logo Freescale Semiconductor
Description PowerQUICC Hardware Specifications
Datasheet MPC875 DatasheetMPC875 Datasheet (PDF)

Freescale Semiconductor Technical Data Document Number: MPC875EC Rev. 4, 08/2007 MPC875/MPC870 PowerQUICC™ Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit core built on Power Architecture™ technology that incorporates memory management units (MMUs) and instruction and data caches. For functional characteristic.

  MPC875   MPC875


Document
Freescale Semiconductor Technical Data Document Number: MPC875EC Rev. 4, 08/2007 MPC875/MPC870 PowerQUICC™ Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit core built on Power Architecture™ technology that incorporates memory management units (MMUs) and instruction and data caches. For functional characteristics of the MPC875/MPC870, refer to the MPC885 PowerQUICC™ Family Reference Manual. To locate published errata or updates for this document, refer to the MPC875/MPC870 product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9 4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. Thermal Calculation and Measurement . . . . . . . . . . 12 8. Power Supply and Power Sequencing . . . . . . . . . . . 14 9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 15 10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 45 13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 47 14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67 15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67 16. Mechanical Data and Ordering Information . . . . . . . 71 17. Document Revision History . . . . . . . . . . . . . . . . . . . 80 © Freescale Semiconductor, Inc., 2003–2007. All rights reserved. Overview 1 Overview The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. Table 1 shows the functionality supported by the MPC875/MPC870. Table 1. MPC875/MPC870 Devices Part MPC875 MPC870 Cache (Kbytes) Ethernet I Cache 8 8 D Cache 10BaseT 81 8— 10/100 2 2 SCC SMC USB Security Engine 1 1 1 Yes — 1 1 No 2 Features The MPC875/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/MPC870 features: • Embedded MPC8xx core up to 133 MHz • Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes • Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch and without conditional execution — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) – Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip emulation debug mode • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 2 Freescale Semiconductor Features • Thirty-two address lines • Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbytes–256 Mbytes) — Selectable write protection — On-chip bus arbitration logic • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on referenc.


D2091 MPC875 MPC870


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