56F805

56F805 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F805 Rev. 16 09/2007 freescale.com Version History Rev. 16 Document Revision History Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.” 56F805 General Description Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-bit words (64KB) Program Flash 512 × 16-bit words (1KB) Program RAM 4K × 16-bit words (8KB) Data Flash 2K × 16-bit words (4KB) Data RAM 2K × 16-bit words (4KB) Boot Flash Up to 64K × 16-bit words (128KB) each of external Program and Data memory Two 6-channel PWM Modules Two 4-channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers JTAG/OnCETM port for debugging 14 Dedicated and 18 Shared GPIO lines 144-pin LQFP Package 6 PWM Outputs Current Sense Inputs 3 Fault Inputs 4 6 PWM Outputs Current Sense Inputs 3 Fault Inputs 4 A/D1 4 A/D2 ADC 4 VREF Quadrature Decoder 0/ 4 Quad Timer A PWMA PWMB Interrupt Controller Quadrature Decoder 1/ Program Memory 4 Quad B Timer 32...