Document
Freescale Semiconductor Data Sheet: Technical Data
Document Number: MMA16xxNKW Rev. 4, 03/2012
DSI Inertial Sensor
The MMA16xxNKW family, a SafeAssure solution, includes the DSI2.5 compatible overdamped Z-axis satellite accelerometers.
Features • ±50g to ±312.5g Nominal Full-Scale Range • Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF • DSI2.5 Compatible with full support of Mandatory Commands • 16 μs internal sample rate, with interpolation to 1 ms • -40°C to 125°C Operating Temperature Range • Pb-Free 16-Pin QFN, 6 by 6 Package • Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
Typical Applications • Airbag Front and Side Crash Detection
MMA16xxNKW
Bottom View
16-PIN QFN CASE 2086-01
Top View
VSS TEST7 TEST6 TEST5
Device MMA1605NKW MMA1606NKW MMA1612NKW MMA1618NKW MMA1631NKW MMA1605NKWR2 MMA1606NKWR2 MMA1612NKWR2 MMA1618NKWR2 MMA1631NKWR2
ORDERING INFORMATION
Axis
Range
Package
Z 50g
2086-01
Z 62.5g
2086-01
Z 125g
2086-01
Z 187g
2086-01
Z 312g
2086-01
Z 50g
2086-01
Z 62.5g
2086-01
Z 125g
2086-01
Z 187g
2086-01
Z 312g
2086-01
Shipping Tubes Tubes Tubes Tubes Tubes
Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel
For user register array programming, please consult your Freescale representative.
16 15 14 13
TEST2 1 TEST3 2 TEST1 3 BUSRTN 4
17 56
12 VSSA 11 CREGA 10 TEST4
9 CREG 78
PCM BUSOUT
BUSIN HCAP
PIN CONNECTIONS
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Application Diagram
Ref Des C1 C3 C4 C5
TEST2 TEST1
BUVSCICN
BUSIN
TEST3
MMA16xxN
TEST4
TEST5
BUSRVTSNS
TEST6
C1
BUSRTN
TEST7
CREG
BUSOUT
C4
CREGA
HCAP
C5
VSSA VSS
PCM
C3
Figure 1. Application Diagram
Type Ceramic Ceramic, Tantalum Ceramic Ceramic
External Component Recommendations
Description
Purpose
100 pF ≤ C1 ≤ 1000 pF 10%, 50V, X7R BUSIN Power Supply Decoupling, ESD
1 μF ≤ C3 ≤ 100 μF, 10%, 50V, X7R Reservoir Capacitor for Keep Alive during Signaling
1 μF, 10%, 10V, X7R 1 μF, 10%, 10V, X7R
Voltage Regulator Output Capacitor (CREG) Voltage Regulator Output Capacitor (CREGA)
Device Orientation
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
Z: 0 g
Z: 0 g
Z: 0 g
xxxxxxx xxxxxxx Z: 0 g EARTH GROUND
Z: +1 g
Figure 2. Device Orientation Diagram
Z: -1 g
MMA16xxNKW 2
Sensors Freescale Semiconductor, Inc.
Internal Block Diagram
BUSIN VSSB
VDSI_REF VDSI_REF
HCAP
DIGITAL VOLTAGE
VREG
REGULATOR
ANALOG VOLTAGE
VREGA
REGULATOR
REFERENCE VREF VOLTAGE
LOW-VOLTAGE RESET
BUSRTN VSS
SERIAL ENCODER
OSCILLATOR
CONTROL LOGIC
OTP FUSE ARRAY
TEST
SELF-TEST INTERFACE
VREG
VREGA
VREG
ΣΔ CONVERTER
CONTROL STATUS IN OUT
DSP
SINC Filter
--------1----–-----z---–---D---------- 3 D × (1 – z–1)
IIR Low-Pass Filter Compensation
PCM Encoder
g-CELL
Figure 3. Block Diagram
HCAP CREG CREGA VSSA
TEST3 TEST4 TEST5 TEST6
PCM
Sensors Freescale Semiconductor, Inc.
MMA16xxNKW 3
1 Pin Connections
VSS TEST7 TEST6 TEST5
16 15 14 13
TEST2 1 TEST3 2 TEST1 3 BUSRTN 4
17 12 VSSA 11 CREGA 10 TEST4
9 CREG
5678
PCM VSSB BUSIN HCAP
Figure 4. Block Diagram
Table 1. Pin Description
Pin
Pin Name
Formal Name
Definition
1 TEST2
Test Pin
This pin must be left unconnected in the application.
2 TEST3
Test Pin
This pin must be grounded in the application.
3 TEST1
Test Pin
This pin must be grounded in the application.
4 BUSRTN
Ground
This pin is the common return for power and signalling.
5 PCM
PCM Output
This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled or disabled via OTP. If unused, this pin must be left unconnected in the application. Reference Section 3.5.3.6.
6 VSSB
Ground
This pin must be grounded in the application.
7 BUSIN
Supply / Comm
This pin is connected to the DSI positive bus node and provides the power supply and communication to the system master. An external capacitor must be connected to between this pin and the BUSRTN pin. Reference Figure 1.
This pin rectifies the supply voltage on the BUSIN pin to create the supply voltage for the device. An external capacitor must 8 HCAP Hold Capacitor be connected between this pin and the BUSRTN pin to store energy for operation during master communication signalling.
Reference Figure 1.
9 CREG
Digital Supply
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1.
10 TEST4
Test Pin
This pin must be grounded in the application.
11 CREGA 12 VSSA 13 TEST5 14 TEST6
Analog Supply Analog GND
Test Pin
Test Pin
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1.
This pin is the power supply return node for analog circuitry.
This pin enables test mode, and provides the SPI programming voltage in test mode. This pin is must be grounded in the a.