Document
GAL26CLV12
Low Voltage E2CMOS PLD Generic Array Logic™
FEATURES Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — Inputs and I/O Interface with Standard 5V TTL Devices • ACTIVE PULL-UPS ON ALL PINS • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • TWELVE OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
Functional Block Diagram
I/CLK
RESET
INPUT 8
I 8 I 8 I 8 I
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (122X52)
OLMC
I/O/Q
10
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I 8 I 8 I 8 I 8
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
PRESET
I/O/Q
Description
The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK I/O/Q I/O/Q
26 25
I
I
2
4
I
I I VCC I I I I
5
I
28
I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q
7
GAL26CLV12D
Top View
23
9
21
11 12 14 16
19 18
I/O/Q
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
I/O/Q
I
I
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
26clv12_02
1
Specifications GAL26CLV12
GAL26CLV12D Ordering Information
Commercial Grade Specifications
Tpd (ns)
5 7.5
Tsu (ns)
3.5 5.5
Tco (ns)
3.5 4.5
Icc (mA)
130 130
Ordering #
GAL26CLV12D-5LJ GAL26CLV12D-7LJ
Package
28-Lead PLCC 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX X X X
GAL26CLV12D Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package J = PLCC
2
Specifications GAL26CLV12
Output Logic Macrocell (OLMC)
The GAL26CLV12D has a variable number of product terms per OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access to ten product terms (pins 19 and 23), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL26CLV12D has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
A R
D Q CLK SP Q
4 TO 1 MUX
2 TO 1 MUX
GAL26CLV12D OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL26CLV12D has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit sett.