GAL6002

GAL6002 High Performance E2CMOS FPLA Generic Array Logic™ Features HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs — UltraMOS® Advanced CMOS Technology ACTIVE PULL-UPS ON ALL PINS LOW POWER CMOS — 90mA Typical Icc E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention UNPRECEDENTED FUNCTIONAL DENSITY — 78 x 64 x 36 FPLA Architecture — 10 Output Logic Macrocells — 8 Buried Logic Macrocells — 20 Input and I/O Logic Macrocells HIGH-LEVEL DESIGN FLEXIBILITY — Asynchronous or Synchronous Clocking — Separate State Register and Input Clock Pins — Functional Superset of Existing 24-pin PAL® and FPLA Devices APPLICATIONS INCLUDE: — Sequencers — State Machine Control — Multiple PLD Device Integration 14 Functional Block Diagram ICLK INPUT CLOCK 2 INPUTS 2-11 14 23 11 { ILMC RESET IOLMC AND OUTPUT ENABLE D E 23 OLMC 0 7 OR D BLMC E { OUTPUTS 14 - 23 OCLK OUTPUT CLOCK Macrocell Names ILMC BLMC OLMC INPUT LOGIC MACROCELL BURIED LOGIC MACROCELL OUTPUT LOGIC MACROCELL IOLMC I/O LOGIC MACROCELL PinNames I0 - I10 ICLK OCLK INPUT INPUT CLOCK OUTPUT CLOCK I/O/Q VCC GND BIDIRECTIONAL POWER (+5V) GROUND Description Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the highest degree of fun...