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ML610Q475 Dataheets PDF



Part Number ML610Q475
Manufacturers LAPIS Semiconductor
Logo LAPIS Semiconductor
Description 8-bit Microcontroller
Datasheet ML610Q475 DatasheetML610Q475 Datasheet (PDF)

ML610Q474/ML610Q475/ML610Q476 8-bit Microcontroller with a Built-in LCD driver FEDL610Q476-02 Issue Date Jul. 31, 2014 GENERAL DESCRIPTION This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with peripheral functions such as the UART, melody driver, Analog compartor, and LCD driver. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. Addition.

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ML610Q474/ML610Q475/ML610Q476 8-bit Microcontroller with a Built-in LCD driver FEDL610Q476-02 Issue Date Jul. 31, 2014 GENERAL DESCRIPTION This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with peripheral functions such as the UART, melody driver, Analog compartor, and LCD driver. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher) and low-power consumption (typically 4.5uA at low-speed operation), enabling volume production by the MTP version. FEATURES • CPU - 8-bit RISC CPU (CPU name: nX-U8/100) - Instruction system: 16-bit length instruction - Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - On-Chip debug function - Minimum instruction execution time 30.5 µs (@ 32.768 kHz system clock) 2 µs (@ 500 kHz system clock) 0.5 µs (@ 2 MHz system clock) • Internal memory - Internal 16KByte flash memory (8K x 16 bits) (including unusable 1K Byte TEST area) - Internal 1KByte RAM (1024 x 8 bits) • Interrupt controller - 1 non-maskable interrupt source: Internal source: 1 (Watchdog Timer) - 22 maskable interrupt sources: Internal source: 12 (Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz, Analog Comparator) External source: 10 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P56) (One interrupt request is generated from P50 to P54, P56 interrupt sources.) • Time base counter - Low-speed time base counter x 1 channel Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) - High-speed time base counter x 1 channel • Watchdog timer - Non-maskable interrupt and reset - Free running - Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s) FEDL610Q476-02 ML610Q474/ML610Q475/ML610Q476 • Timers - 8 bits x 6 channels [also available is 16-bit x 3 configuration (using Timers 0-1, 2-3, or C-D) ] - Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only) - The timer C and timer D are controlled by the external trigger. - The timer C and timer D are used for the one-shot timer mode. • Capture - Time base capture x 2 channels (4096 Hz to 32 Hz) • UART - TXD/RXD × 1 channel - Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - Positive logi.


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