SPC58NE84E7

SPC58NE84E7, SPC58NE84C3 32-bit Power Architecture® microcontroller for automotive ASIL-D applications Data brief - preliminary data LFBGA292 (17 x 17 x 1.7 mm) eLQFP176 (24 x 24 x 1.4 mm) Features  Two 32-bit Power Architecture® VLE compliant CPU core (e200z4d), dual issue, one of them being paired in lockstep – Single-precision floating point operations – 8 kB I-Cache and 4 kB D-Cache – 16 kB local instruction SRAM and 64 kB local data SRAM  One 32-bit Power Architecture® VLE compliant CPU core (e200z4d), dual issue, paired in lockstep – Single-precision floating point operations – Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction support for digital signal processing (DSP) – 8 kB I-Cache – 16 kB local instruction SRAM and 32 kB local data SRAM  6320 kB on-chip flash memory – Supporting EEPROM emulation (256 kB) – 2 Flash Controller supporting true ReadWhile-Read Flash access (RWR)  608 kB on-chip general-purpose SRAM (+160 kB data RAM included in the CPUs)  Multi-channel direct memory access controller (eDMA) with 96 channels, paired in lock-step  Dual phase-locked loops, including one frequency-modulated  Hardware Security Module (HSM) to provide robust integrity checking of flash memory  Generic Timer Module (GTM) – Intelligent complex timer module – 144 channels (40 inputs/104 outputs) – 5 programmable fine grain multi-threaded cores – 61 kB of dedicated SRAM – Hardware support for engine control, motor control and safety related a...