Document
HD74HC4052, HD74HC4053
Dual 4-channel Analog Multiplexers/Demultiplexers Triple 2-channel Analog Multiplexers/Demultiplexers
REJ03D0649-0200 (Previous ADE-205-536)
Rev.2.00 Mar 30, 2006
Description
HD74HC4052: This device connects together the outputs of 4 switches in two sets, thus achieving a pair of 4 channel multiplexers. The binary code placed on the A, and B select lines determine which switch in each 4 channel section is “on”, connecting one of the four inputs in each section to its common output. This enables the implementation of a 4 channel differential multiplexer.
HD74HC4053: This device contains 6 switches whose outputs are connected together in pairs, thus implementing a triple 2 channel multiplexer, or the equivalent of 3 single-pole-double throw configuration. Each of the A, B, or C select lines independently controls one pair of switches, selecting one of the two switches to be “on”.
Features
• High Speed Operation
• Wide Operating Voltage: VCC = 2 to 6 V • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) • Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74HC4052P HD74HC4053P
DILP-16 pin
PRDP0016AE-B (DP-16FV)
P
HD74HC4052FPEL SOP-16 pin (JEITA)
HD74HC4053FPEL
PRSP0016DH-B (FP-16DAV)
FP
HD74HC4052RPEL SOP-16 pin (JEDEC)
HD74HC4053RPEL
PRSP0016DG-A (FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Function Table
Control Inputs
Select
Inhibit
C*1
B
LLL
LLL
L LH
L LH
LHL
LHL
L HH
L HH
HXX
Note: 1. Not applicable for HD74HC4052
X = Irrelevant
A L H L H L H L H X
HD74HC4052 Y0 X0 Y1 X1 Y2 X2 Y3 X3
— — — — —
ON Switch HD74HC4053
Z0 Y0 Z0 Y0 Z0 Y1 Z0 Y1 Z1 Y0 Z1 Y0 Z1 Y1 Z1 Y1
—
X0 X1 X0 X1 X0 X1 X0 X1
Rev.2.00 Mar 30, 2006 page 1 of 11
HD74HC4052, HD74HC4053
Pin Arrangement
HD74HC4052
Y0 1 Y2 2 Y3 Y3 4 Y1 5 Inhibit 6 VEE 7 GND 8
Y0 Y2
X2
Y X1
Y3 X
Y1 X0
Inhibit
X3
A B
(Top view)
16 VCC 15 X2 14 X1 13 X 12 X0 11 X3 10 A 9B
HD74HC4053
Y1 1 Y0 2 Z1 3 Z4 Z0 5 Inhibit 6 VEE 7 GND 8
Y1 Y0
Y
Z1 X
Z X1
Z0 X0
Inhibit
A
B C
(Top view)
16 VCC 15 Y 14 X 13 X1 12 X0 11 A 10 B 9C
Rev.2.00 Mar 30, 2006 page 2 of 11
HD74HC4052, HD74HC4053
Block Diagram
HD74HC4052
Inh A B
X0 X1 X2 X3 Y0 Y1 Y2 Y3
VCC
Level Converter
Binary to 1-of-4 Decoder
with Inhibit
GND
VEE
HD74HC4053
VCC
Inh A Level B Converter C
Binary to 1-of-2 Decoder with Inhibit
GND
VEE
X0 X1 Y0 Y1 Z0 Z1
X Y
X Y Z
Absolute Maximum Ratings
Item Supply voltage
Control input voltage Switch I/O voltage Supply current
Switch I/O current (per pin) Control input diode current Switch I/O diode current Power dissipation Storage temperature range
(VCC) (GND)
Symbol VCC
VCC – VEE VIN VI/O ICC IGND II/O IIK IIOK PT Tstg
Rating –0.5 to +7.0 –0.5 to +7.0 GND – 0.5 to VCC + 0.5 VEE – 0.5 to VCC + 0.5
+50 –50 ±25 ±20 ±20 500 –65 to +150
Rev.2.00 Mar 30,.