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BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (binary.)
The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge.
BCD (Modulo 10)
Binary (Modulo 16)
Asynchronous Reset
LS160A
LS161A
Synchronous Reset
LS162A
LS163A
• Synchronous Counting and Loading • Two Count Enable Inputs for High Speed Synchronous Expansion • Terminal Count Fully Decoded • Edge-Triggered Operation • Typical Count Rate of 35 MHz • ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9
1234 *R CP P0 P1
56
78
P2 P3 CEP GND
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
*MR for LS160A and LS161A *SR for LS162A and LS163A
PIN NAMES
PE
P0 – P3 CEP
CET
CP
MR
SR
Q0 – Q3 TC
Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs (Note b) Terminal Count Output (Note b)
LOADING (Note a)
HIGH
LOW
1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L.
0.5 U.L. 0.25 U.L. 0.25 U.L.
0.5 U.L. 0.25 U.L. 0.25 U.L.
0.5 U.L. 5 (2.5) U.L. 5 (2.5) U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A
BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS
LOW POWER SCHOTTKY
16 1
J SUFFIX CERAMIC CASE 620-09
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
D SUFFIX SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC
LOGIC SYMBOL
934 56
PE P0 P1 P2 P3 7 CEP
10 CET
TC 15
2 CP *R Q0 Q1 Q2 Q3
1 14 13 12 11
VCC = PIN 16 GND = PIN 8
*MR for LS160A and LS161A *SR for LS162A and LS163A
FAST AND LS TTL DATA 5-278
SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A
STATE DIAGRAM LS160A • LS162A
0123
15
14
13
12 11 10
9
4 5 6 7 8
LS161A • LS163A 01234
15 5
14 6
13 7
12 11 10 9
8
LOGIC EQUATIONS
Count Enable = CEP • CET • PE TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3 TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 Preset = PE • CP + (rising clock edge) Reset = MR (LS160A & LS161A) Reset = SR • CP + (rising clock edge) Reset = (LS162A & LS163A)
NOTE: The LS160A and LS162A can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses.
FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET • CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits.
The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for
the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state.
The LS160A and LS162A count modulo 10 following a binary coded decimal (BCD) sequence. They generate a TC output when the CET input is HIGH while the counter is in state 9 (.