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TC74HC4538AP/AF/AFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC4538AP, TC74HC4538AF, TC74HC4538AFT
Dual Retriggerable Monostable Multivibrator
The TC74HC4538A is a high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
There are two trigger inputs, A input (positive edge input), and B input (negative edge input). These inputs are valid for a slow rise/fall time signal (tr = tf = 1 s) as they are schmitt trigger inputs. After triggering, the output stays in a MONOSTABLE state for the time period determined by the external resistor and capacitor (RX, CX). A low level at CD input breaks this STABLE STATE. In the MONOSTABLE state, if a new trigger is applied, it makes the MONOSTABLE period longer (retrigger mode).
Limitations for CX and RX are as follows: External capacitor CX ........... No limitation External resistor RX .............. VCC = 2.0 V more than 5 kΩ VCC ≥ 3.0 V more than 1 kΩ
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features (Note)
• High speed: tpd = 25 ns (typ.) at VCC = 5 V • Low power dissipation
Stand by state: ICC = 4 μA (max) at Ta = 25°C Active state: ICC = 300 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH −∼ tpHL • Wide operating voltage range: VCC (opr) = 2 V to 6 V • Pin and function compatible with 4538B
Note: In the case of using only one circuit, CD should be tied to GND, T1·T2·Q· Q should be tied to OPEN, the other inputs should be tied to VCC or GND.
TC74HC4538AP
TC74HC4538AF
TC74HC4538AFT
Weight DIP16-P-300-2.54A SOP16-P-300.1.27A TSSOP16-P-0044-0.65A
: 1.00 g (typ.) : 0.18 g (typ.) : 0.06 g (typ.)
Start of commercial production
1987-11
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Pin Assignment
1T1 1 1T2 2 1CD 3 1A 4 1B 5 1Q 6 1Q 7 GND 8
(top view)
16 VCC 15 2T1 14 2T2 13 2CD 12 2A 11 2B 10 2Q 9 2Q
Truth Table
Inputs
A
B CD
H
H
X
L
H
H
X
H
L
H
X
X
L
X: Don’t care
Outputs
Q
Q
L
H
L
H
L
H
Note
Output Enable Inhibit Inhibit Output Enable Reset
TC74HC4538AP/AF/AFT
IEC Logic Symbol
1A (4) 1B (5) 1CD (3) 1T1 (1) 1T2 (2)
2A (12) 2B (11) 2CD (13) 2T1 (15) 2T2 (14)
&
R CX RX/CX
&
R CX RX/CX
(6) 1Q (7) 1Q
(10) 2Q (9) 2Q
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2016-12-02
Block Diagram (Note)
TC74HC4538AP/AF/AFT
A4 B5
DX
CX
RX 12
VCC
T1 T2
6Q
7Q
3 CD
A 12 B 11
DX
CX
RX 15 14
VCC
T1 T2
10 Q
13 CD
9Q
Note: Note:
CX, RX, DX are external capacitor, resistor, and diode, respectively.
External clamping diode, DX
The external capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied. Supply voltage is turned off and CX is discharged mainly through the internal (parasitic) diode. If CX is sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC by rush current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20 mA.
In the case of a large CX, the limitation of fall time of the supply voltage is determined as follows:
tf ≥ (VCC - 0.7) CX/20 mA (tf is the time from the voltage supply turning off to the level of supply voltage reaching 0.4 VCC.)
In the care of a system that does not satisfy the above condition, an external clamping diode is needed to protect the IC from rush current.
3
2016-12-02
System Diagram
VCC QP
VrefL C1
T2 QN
T1
VCC
DR Q
A
B
CK Q
F/F
CD
Timing Chart
A B
T2 CD
Q
Q
twOUT
twOUT
TC74HC4538AP/AF/AFT
VrefH C2
trr twOUT + trr
Q Q
VIH VIL VIH VIL VCC VrefH VrefL GND VIH VIL VOH VOL VOH VOL
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2016-12-02
TC74HC4538AP/AF/AFT
Functional Description
(1) Stand-by state The external capacitor is fully charge to VCC in the stand-by state. That means, before triggering,
QP and QN transistors which are connected to the T2 node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies stop their operation. The total supply current is only leakage current. (2) Trigger operation
Trigger operation is effective in either of the following two cases. One is the condition where the A input is low, and the B input has a falling signal. The other, where the B input is high, and the A input has a rising signal.
After trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level at the T2 node drops. If the T2 voltage level falls to the internal reference voltage VrefL, the output of C1 becomes low. The flip-flop is then reset and QN turns off. At that moment C1 stops.