Document
SSFP5N20
StarMOST Power MOSFET
■ Extremely high dv/dt capability ■ Low Gate Charge Qg results in
Simple Drive Requirement ■ 100% avalanche tested ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeatability
Description
StarMOS is a new generation of high voltage N–Channel enhancement mode power MOSFETs. This new technology minimises the JFET effect, increases packing density and reduces the on-resistance. StarMOS also achieves faster switching speeds through optimised gate layout with planar stripe DMOS technology.
Application
■ Switching application
VDSS = 200V ID25 =5A RDS(ON) =0.8Ω
Pin1–Gate Pin2–Drain Pin1–Source
Absolute Maximum Ratings
ID@Tc=25ْ C ID@Tc=100ْC
Parameter Continuous Drain Current,VGS@10V Continuous Drain Current,VGS@10V
IDM Pulsed Drain Current ① PD@TC=25ْC Power Dissipation
Linear Derating Factor
VGS Gate-to-Source Voltage
EAS Single Pulse Avalanche Energy ②
IAR Avalanche Current ①
EAR Repetitive Avalanche Energy ①
dv/dt
Peak Diode Recovery dv/dt ③
TJ Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque,6-32 or M3 screw
Max. 5.0 3.0 20 40 0.32 ±20 85 6.0 5.0
-
–25 to +150
300(1.6mm from case) 10 Ibf●in(1.1N●m)
Units
A
W W/ْ C
V mJ A mJ V/ns
ْC
Thermal Resistance
Parameter
Min. Typ. Max.
RθJC RθCS RθJA
Junction-to-case Case-to-Sink,Flat,Greased Surface Junction-to-Ambient
— — —
— 3.12 - 0.5 — 80
Units ْC/W
1
SSFP5N20
StarMOST Power MOSFET
Electrical Characteristics @TJ=25 ْC(unless otherwise specified)
Parameter
Min. Typ. Max. Units
Test Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage 200
△V(BR)DSS/△TJ Breakdown Voltage Temp.Coefficient —
— -
— V VGS=0V,ID=250μA — V/ْC Reference to 25ْC,ID=1mA
RDS(on) VGS(th)
Static Drain-to-Source On-resistance —
Gate Threshold Voltage
2.0
- —
0.8 Ω VGS=10V,ID=2.5A 4.0 V VDS=VGS,ID=250μA
gfs
Forward Transconductance
1.3 -
— S VDS=10V,ID=2.5A
— — 250
VDS=Rated VDSS,VGS=0V
IDSS
Drain-to-Source Leakage current
—
—
μA VDS=0.8×Rated VDSS,
1000
VGS=0V,TJ=125ْC
Gate-to-Source Forward leakage
— — 500
VGS=20V
IGSS
Gate-to-Source Reverse leakage
nA
— — -500
VGS=-20V
Qg Total Gate Charge
— 11 15
VGS=10V
Qgs Gate-to-Source charge
— 5.0 — nC ID=6.0A
Qgd
Gate-to-Drain("Miller") charge
— 6.0 —
VDD=45V
td(on)
Turn-on Delay Time
— - 40
VDD=100V
tr td(off) tf
Rise Time Turn-Off Delay Time Fall Time
— - 60
ID=2.5A
— - 100 nS VGS=10V
— - 60
RGEN=50Ω RGS=50Ω
LD Internal Drain Inductance
— 4.5 —
Between lead, 6mm(0.25in.)
nH from package
LS
Internal Source Inductance
- 7.5 —
and center of
die contact
Ciss Input Capacitance
— 600 —
VGS=0V
Coss
Output Capacitance
— 300 — pF VDS=25V
Crss
Reverse Transfer Capacitance
— 80 —
f=1.0MHZ See Figure 5
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Test Conditions
Continuous Source Current . IS
(Body Diode)
Pulsed Source Current ISM (Body Diode) ①
.
VSD Diode Forward Voltage
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
—
— — - -
— 5.0
— 20
— 1.8 350 -
2.3 -
MOSFET symbol showing the A integral reverse p-n junction diode. V TJ=25ْC,IS=5.0A,VGS=0V ④ nS TJ=25ْC,IS=5.0A nC di/dt=25A/μs ④
ton Forward Turn-on Time
Intrinsic turn-on time is negligible (turn-on is dominated by Ls + LD)
Notes: ① Repetitive rating;pulse width limited by
max.junction temperature(see figure 11)
② L =6.18mH, IAS = 5.0A, VDD = 10V,
RG = 25Ω, Starting TJ = 25°C
③ ISD≤5A,di/dt≤60A/μS,VDD≤V(BR)DSS, TJ≤150ْ C
④ Pulse width≤300μS; duty cycle≤2%
2
.