Document
MM54HCT688 MM74HCT688 8-Bit Magnitude Comparator (Equality Detector)
February 1988
MM54HCT688 MM74HCT688 8-Bit Magnitude Comparator (Equality Detector)
General Description
This equality detector utilizes advanced silicon-gate CMOS technology to compare bit for bit two 8-bit words and indicate whether or not they are equal The PeQ output indicates equality when it is low A single active low enable is provided to facilitate cascading of several packages and enable comparison of words greater than 8 bits
This device is useful in memory block decoding applications where memory block enable signals must be generated from computer address information
The comparator combines the low power consumption of CMOS but inputs are compatible with TTL logic levels and the output can drive 10 low power Schottky equivalent loads
MM54HCT MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices These parts are also plug in replacements for LSTTL devices and can be used to reduce power consumption in existing designs
All inputs are protected from damage due to static discharge by diodes to VCC and ground
Features
Y TTL input compatible Y Typical propagation delay 20 ns Y Low quiescent current 80 mA maximum (74HCT Series) Y Large output current 4 mA Y Same as HCT521
Logic Diagrams
C1995 National Semiconductor Corporation TL F 5371
TL F 5371 – 2 RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD)
(Note 3) S O Package only
b0 5 to a7 0V b1 5 to VCCa1 5V b0 5 to VCCa0 5V
g20 mA g25 mA g50 mA b65 C to a150 C
600 mW 500 mW
Lead Temperature (TL) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage (VIN VOUT)
Operating Temp Range (TA) MM74HCT688 MM54HCT688
Min 45 0
b40 b55
Input Rise or Fall Times (tr tf)
Max 55 VCC
a85 a125
500
Units V V
C C
ns
DC Electrical Characteristics (VCCe5V g10% unless otherwise specified)
Symbol
Parameter
Conditions
TAe25 C Typ
74HCT
54HCT
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level Input Voltage
20 20
20 V
VIL Maximum Low Level Input Voltage
08 08
08 V
VOH
Minimum High Level VINe0 8V or 2 0V
Output Voltage
lIOUTle20 mA
VCC VCCb0 1
l lIOUT e4 0 mA VCCe4 5V 4 2
3 98
l lIOUT e4 8 mA VCCe5 5V 5 7
4 98
VOL Maximum Low Level VINeV0 8V or 2 0V
Voltage
lIOUTle20 mA
0 01
l lIOUT e4 0 mA VCCe4 5V 0 2
0 26
l lIOUT e4 8 mA VCCe5 5V 0 2
0 26
IIN
Maximum Input
VINeVCC or GND
Current
g0 1
VCCb0 1 3 84 4 84
01 0 33 0 33 g1 0
VCCb0 1 37 47
01 04 04 g1 0
V V V
V V V mA
ICC Maximum Quiescent VINeVCC or GND
Supply Current
IOUTe0 mA
8 0 80
160 mA
VINe2 4V or 0 5V (Note 4) 0 3 0 4
0 5 mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 Measured per pin All other inputs held at VCC or ground
2
AC Electrical Characteristics
VCC e 5V TA e 25 C CL e 15 pF tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions Typ
tPHL
Maximum Propagation
Delay - P or Q to Output
tPLH
Maximum Propagation
Delay - P or Q to Output
tPHL
Maximum Propagation
Delay - Enable to Output
tPHL
Maximum Propagation
Delay - Enable to Output
19 13 13 10
Guaranteed Limit 30
22
20
18
Units ns ns ns ns
AC Electrical Characteristics
VCC e 5V g10% CL e 50 pF tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TAe25 C
74HCT TAeb40 to 85 C
54HCT TAeb55 to 125 C
Typ Guaranteed Limits
Units
tPHL
Maximum Propagation
Delay - P or Q to Output
23 35
44
53 ns
tPLH
Maximum Propagation
Delay - P or Q to Output
16 24
30
36 ns
tPHL
Maximum Propagation
Delay - Enable to Output
16 24
30
36 ns
tPLH
Maximum Propagation
Delay - Enable to Output
11 20
25
30 ns
tTHL tTLH
Maximum Output Rise and Fall Time
8 15
19
22 ns
CPD Power Dissipation Capacitance (Note 5)
45
pF
CIN Maximum Input Capacitance
5 10
10
10 pF
Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC a ICC
Connection Diagram
Truth Table
Dual-In-Line Package
Inputs
Data PQ
Enable G
PeQ PlQ PkQ
X
L L L H
PeQ
L H H H
Top View Order Number MM54HCT688 or MM74HCT688
TL F 5371 – 1
3
MM54HCT688 MM74HCT688 8-Bit Magnitude Comparator (Equality Detector)
Physical Dimensions inches (millimeters)
O.