MBM29F040C-70

FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 4M (512K × 8) BIT DS05-20842-4E MBM29F040C-55/-70/-90 s FEATURES www.DataSheet4U.com Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture 8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase. Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector Embedded Program™ Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Low VCC write inhibit ≤ 3.2 V Sector protection Hardware method disables any combination of sectors from write or erase operations Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc. MBM29F040C-55/-70/-90 s PACKAGE 32-pin Plastic QFJ (PLCC) Marking Side 32-pin Plastic TSOP (I) Marking Side (LCC-32P-M02) 32-pin Pla...