Document
OptiMOS®-T2 Power-Transistor
Features • N-channel - Enhancement mode • AEC Q101 qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green Product (RoHS compliant) • 100% Avalanche tested
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
Product Summary V DS R DS(on),max (SMD version) ID
60 V 2.8 mΩ 120 A
PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1
Type IPB120N06S4-03 IPI120N06S4-03 IPP120N06S4-03
Package PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1
Marking 4N0603 4N0603 4N0603
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Continuous drain current1)
I D T C=25°C, V GS=10V
T C=100°C, V GS=10V2)
Pulsed drain current2)
I D,pulse T C=25°C
Avalanche energy, single pulse2) E AS I D=60A
Avalanche current, single pulse I AS -
Gate source voltage
V GS
-
Power dissipation
P tot T C=25°C
Operating and storage temperature T j, T stg -
IEC climatic category; DIN IEC 68-1 -
-
Value 120
120
480 392 120 ±20 167 -55 ... +175 55/175/56
Unit A
mJ A V W °C
Rev. 1.0
page 1
2009-03-23
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
Parameter
Symbol
Conditions
min.
Values typ.
Unit max.
Thermal characteristics2)
Thermal resistance, junction - case R thJC
Thermal resistance, junction ambient, leaded
R thJA
-
- - 0.9 K/W - - 62
SMD version, device on PCB
R thJA
minimal footprint 6 cm2 cooling area3)
-
- 62 - 40
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0V, I D= 1mA
60 -
-V
Gate threshold voltage
V GS(th) V DS=V GS, I D=120µA
2.0
3.0
4.0
Zero gate voltage drain current
I DSS
V DS=60V, V GS=0V, T j=25°C
- 0.01 1 µA
Gate-source leakage current Drain-source on-state resistance
V DS=60V, V GS=0V, T j=125°C2)
I GSS
V GS=20V, V DS=0V
R DS(on) V GS=10V, I D=100A
- 10 200
- - 100 nA - 2.6 3.2 mΩ
V GS=10V, I D=100A, SMD version
-
2.3 2.8
Rev. 1.0
page 2
2009-03-23
Parameter
Dynamic characteristics2) Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time
Gate Charge Characteristics2) Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage
Reverse Diode Diode continous forward current2) Diode pulse current2)
Diode forward voltage
Reverse recovery time2)
Symbol
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
Conditions
min.
Values typ.
Unit max.
C iss C oss Crss t d(on) tr t d(off) tf
V GS=0V, V DS=25V, f =1MHz
V DD=30V, V GS=10V, I D=120A, R G=3.5Ω
- 10120 13150 pF - 2480 3220 - 100 200 - 40 - ns - 10 - 80 - 15 -
Q gs Q gd Qg V plateau
V DD=48V, I D=120A, V GS=0 to 10V
- 54 70 nC - 13.5 27 - 125 160 - 5.3 - V
IS I S,pulse
V SD
T C=25°C
V GS=0V, I F=100A, T j=25°C
t rr
V R=30V, I F=120A, di F/dt =100A/µs
- - 120 A - - 480 0.6 0.95 1.3 V
- 115 - ns
Reverse recovery charge2)
Q rr
- 110 - nC
1) Current is limited by bondwire; with an R thJC = 0.9K/W the chip is able to carry 181A at 25°C.
2) Specified by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air.
Rev. 1.0
page 3
2009-03-23
1 Power dissipation P tot = f(T C); V GS ≥ 6 V
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
2 Drain current I D = f(T C); V GS ≥ 6 V; SMD
180 140
160 120
140 100
120
100 80
P tot [W] I D [A]
80 60
60 40
40
20 20
00
0 50 100 150 200
0 50 100 150
T C [°C]
T C [°C]
3 Safe operating area I D = f(V DS); T C = 25 °C; D = 0; SMD parameter: t p
1000
4 Max. transient thermal impedance Z thJC = f(t p) parameter: D =t p/T
101
1 µs
I D [A] Z thJC [K/W]
100 10
10 µs 100 µs
1 ms
100
0.5
10-1
0.1 0.05
10-2
0.01
200
single pulse
1 0.1
1 10 V DS [V]
100
10-3 10-6
10-5
10-4
10-3
10-2
10-1
100
t p [s]
Rev. 1.0
page 4
2009-03-23
I D [A] R DS(on) [mΩ]
5 Typ. output characteristics I D = f(V DS); T j = 25 °C; SMD parameter: V GS
480
10 V 8 V 7 V
400
320
240
160
80
0 01234 V DS [V]
7 Typ. transfer characteristics I D = f(V GS); V DS = 6V parameter: T j
480
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
6 Typ. drain-source on-state resistance R DS(on) = f(I D); T j = 25 °C; SMD parameter: V GS
10
5V
9
6V
8
7
6
6V
5
4 7V
3
5V
2
8V 10 V
56
1 0 80 160 240 320 400 480 I D [A]
8 Typ. drain-source on-state resistance R DS(on) = f(T j); I D = 100 A; V GS = 10 V; SMD
5
4.5 400
4 320
3.5
240 3
I D [A] R DS(on) [mΩ]
160
80
0 3
175 °C
25 °C -55 °C
45 V GS [V]
6
2.5
2
1.5
7
1 -60 -20 20
60 100 140 180
T j [°C]
Rev. 1.0
page 5
2009-03-23
9 Typ. gate threshold voltage V GS(th) = f(T j); V GS = V DS parameter: I D
4
IPB120N06S4-03 IPI120N06S4-03, IPP120N06S4-03
10 Typ. capacitances C = f(V DS); V GS = 0 V; f = 1 MHz
105
V GS(th) [V] C [pF]
3.5
1200 µA
3
120 µA
2.5
2
104 103 102
Ciss Coss
Crss
1.5 -60 -20 20 60 100 140 180 T j [°C]
110011 0
5 10 15 20 25 30 V D.