IS45S16800E

IS45S81600E IS45S16800E 1162M8Mxb8S, Y8NMCxH1R6O NOUS DRAM DECEMBER 2011 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply IS45S81600E Vdd Vddq 3.3V 3.3V IS45S16800E 3.3V 3.3V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 4096 refresh cycles every 16 ms (A2 grade) or 64 ms (A1 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Automotive Temperature Range: Option A1: -40oC to +85oC Option A2: -40oC to +105oC OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized as follows. IS45S81600E 4M x8 x4 Banks 54-pin TSOPII IS45S16800E 2M x16 x4 Banks 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 6 7 10 10 166 143 1...