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NAND128-A Dataheets PDF



Part Number NAND128-A
Manufacturers Numonyx
Logo Numonyx
Description SLC NAND flash memories
Datasheet NAND128-A DatasheetNAND128-A Datasheet (PDF)

NAND128-A NAND256-A 128-Mbit or 256-Mbit, 528-byte/264-word page, 3 V, SLC NAND flash memories Features • High density NAND flash memories – Up to 256-Mbit memory array – Up to 32-Mbit spare area – Cost effective solutions for mass storage applications • NAND interface – x8 or x16 bus width – Multiplexed address/ data – Pinout compatibility for all densities • Supply voltage – VDD = 2.7 to3.6 V • Page size – x8 device: (512 + 16 spare) bytes – x16 device: (256 + 8 spare) words • Block size – x.

  NAND128-A   NAND128-A


Document
NAND128-A NAND256-A 128-Mbit or 256-Mbit, 528-byte/264-word page, 3 V, SLC NAND flash memories Features • High density NAND flash memories – Up to 256-Mbit memory array – Up to 32-Mbit spare area – Cost effective solutions for mass storage applications • NAND interface – x8 or x16 bus width – Multiplexed address/ data – Pinout compatibility for all densities • Supply voltage – VDD = 2.7 to3.6 V • Page size – x8 device: (512 + 16 spare) bytes – x16 device: (256 + 8 spare) words • Block size – x8 device: (16 K + 512 spare) bytes – x16 device: (8 K + 256 spare) words • Page read/program – Random access: 12 µs (3V)/15 us (1.8V) (max) – Sequential access: 50 ns (min) – Page program time: 200 µs (typ) • Copy back program mode – Fast page copy without external buffering • Fast block erase – Block erase time: 2 ms (typical) • Status register • Electronic signature • Chip enable ‘don’t care’ – Simple interface with microcontroller • Security features – OTP area – Serial number (unique ID) TSOP48 12 x 20mm FBGA VFBGA55 8 x 10 x 1.05mm • Hardware data protection – Program/erase locked during power transitions • Data integrity – 100,000 program/erase cycles – 10 years data retention • RoHS compliance – Lead-free components are compliant with the RoHS directive • Development tools – Error correction code software and hardware models – Bad blocks management and wear leveling algorithms – File system OS native reference software – Hardware simulation models October 2012 Rev. 17 1/60 www.numonyx.com 1 Contents Contents NAND128-A, NAND256-A 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/60 NAND128-A, NAND256-A Contents 6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..


SCK-1201 NAND128-A NAND256-A


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