>> >>
>> >>
GR3281H (32K x 8) NON-VOLATILE RAM
Address CE OE
DOUT
READ CYCLE
< tRC
>
< < t AtACCCS >>
< tOE > ...
>> >>
>> >>
GR3281H (32K x 8) NON-VOLATILE RAM
Address CE OE
DOUT
READ CYCLE
< tRC
>
< < t AtACCCS >>
< tOE >
LZ> < < tOHZ >
Address CE WE
DOUT DIN
Address CE WE
DOUT DIN
WRITE CYCLE 1
< tWC
>
< tWP >
tWHZ>
< tWR >
<
WRITE CYCLE 2
< tWC
>
< tWP >< tWR >
t WHZ>
<
TIMING (nS-nano seconds)
Symbol t RC t ACC t ACS t OE t CLZ t OLZ t OH t CHZ t OHZ
Read Cycle Parameter Read cycle time Access time CE to output valid OE to output valid CE to output active OE to output active Output hold time CE to output disable OE to output disable
70nS Min Max 70
70 70 35 10 10 10 25 25
Symbol t WC t WP t AS t WR t WHZ t OW t DS t DH
Write Cycle Parameter Write cycle time Write pulse width Address setup time Write recovery time WR to output disable Output active from WR Data setup time Data HOLD TIME
70nS Min Max 70 50
0 0
20 5 30 0
Notes 1. WE must be high during address transitions. 2. A Write occurs during the overlap of a low CE
and a low WE. 3. WE is high for a read cycle.
REPLACES 62256., 43256., 55257., etc.
DIMENSIONS (mm)
< 37 >
< 18 >
7.3
> < 0.5
> <2.5
4
> < 0.38 < 15.24 >
2000/95/EC
http://www.greenwichinst.co.uk
ISSUE 4 OCT 2005
GR3281H (32K x 8) NON-VOLATILE RAM
Address CE OE
DOUT
READ CYCLE
< tRC
>
<
< t AtACCCS
> >
< tOE > LZ> < < tOHZ >
Address CE WE
DOUT DIN
Address
CE WE DOUT DIN
WRITE CYCLE 1
< tWC
>
< tWP >
tWHZ>
< tWR >
<
Similar Datasheet
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