CY7C1024DV33

CY7C1024DV33 3-Mbit (128 K × 24) Static RAM Features I Highspeed Ë tAA = 10 ns I Low activepower Ë ICC = 175 mA at f= 100 MHz I Low CMOS standbypower Ë ISB2 = 25 mA I Operatingvoltages of3.3 ±0.3 V I 2.0 V data retention I Automatic power-downwhendeselected I Transistor-transistorlogic (TTL) compatibleinputs andoutputs I EasymemoryexpansionwithCE1, CE2, andCE3 features I AvailableinPb-freestandard119-ballPBGA FunctionalDescription TheCY7C1024DV33 is a highperformanceCMOS static RAM organizedas 128 K words by24 bits. This devicehas an automatic power-downfeaturethat significantlyreduces power consum ption when deselected. Towritetothedevice, enablethechip(CE1 LOW, CE2 HIGH, andCE3 LOW), whileforcingtheWriteEnable(WE) input LOW. Toreadfrom thedevice, enablethechipbytakingCE1 LOW, CE2 HIGH, andCE3 LOW whileforcingtheOutput Enable(OE) LOW andtheWriteEnable(WE) HIGH. SeetheTruthTableonpage 7 fora completedescriptionofReadandWritemodes. The24 I/O pins (I/O0 toI/O23) areplacedina highimpedance statewhenthedeviceis deselected(CE1 HIGH, CE2 LOW, or CE3 HIGH) orwhentheoutput enable(OE) is HIGH duringa writeoperation. (CE1 LOW, CE2 HIGH, CE3 LOW, andWE LOW). Logic Block Diagram INPUT BUFFER A(9:0) 128K x24 ARRAY I/O0 –I/O23 ROW DECODER SENSE AMPS COLUMN DECODER A(16:10) CONTROL LOGIC CE1, CE2, CE3 WE OE CypressSem iconductorCorporation 198 ChampionCourt Document Number:001-08353 Rev. *E SanJose, CA 95134-1709 408-943-2600 RevisedSeptember29, 2011 CY7C1024DV33 Select...