Document
VDS RDS(on) max
(@VGS = 4.5V)
Qg (typical) ID
(@TA = 25°C)
IRF7807TRPbF-1 IRF7807ATRPbF-1
HEXFET® Chip-Set for DC-DC Converters
30 V 25 mΩ 12 nC 8.3 A
S1 S2 S3 G4
A 8D 7D 6D 5D
Top View
SO-8
Features Industry-standard pinout SO-8 Package
Compatible with Existing Surface Mount Techniques RoHS Compliant, Halogen-Free
MSL1, Industrial qualification
Benefits ⇒ Multi-Vendor Compatibility
Easier Manufacturing Environmentally Friendlier
Increased Reliability
Base Part Number
IRF7807PbF-1 IRF7807APbF-1
Package Type SO-8
Standard Pack
Form
Quantity
Tape and Reel
4000
Tape and Reel
4000
Orderable Part Number
IRF7807TRPbF-1 IRF7807ATRPbF-1
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source
25°C
Current (VGS ≥ 4.5V) Pulsed Drain Current
70°C
Power Dissipation
25°C
70°C
Junction & Storage Temperature Range
Continuous Source Current (Body Diode)
Pulsed source Current
Symbol VDS VGS ID
IDM PD
TJ, TSTG IS ISM
IRF7807
IRF7807A
30
±12
8.3 8.3
6.6 6.6
66 66
2.5
1.6
–55 to 150
2.5 2.5
66 66
Units V A
W °C A
Thermal Resistance Parameter Maximum Junction-to-Ambient
RθJA
Max. 50
Units °C/W
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October 16, 2014
IRF7807/ATRPbF-1
Electrical Characteristics
Parameter
Drain-to-Source Breakdown Voltage*
V(BR)DSS
Static Drain-Source on Resistance*
RDS(on)
Gate Threshold Voltage*
Drain-Source Leakage Current*
VGS(th) IDSS
IRF7807 Min Typ Max 30 – –
17 25
1.0 30 150
IRF7807A Min Typ Max Units 30 – – V
17 25 mΩ
1.0 V 30 μA 150
Conditions VGS = 0V, ID = 250μA
VGS = 4.5V, ID = 7A
VDS = VGS, ID = 250μA VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, Tj = 100°C
Gate-Source Leakage Current*
IGSS
±100
±100 nA VGS = ±12V
Total Gate Charge*
Pre-Vth Gate-Source Charge
Qg Qgs1
12 17 2.1
12 17 2.1
VGS = 5V, ID = 7A VDS = 16V, ID = 7A
Post-Vth Gate-Source Charge
Qgs2
0.76
0.76 nC
Gate to Drain Charge
Switch Charge* (Qgs2 + Qgd) Output Charge* Gate Resistance
Turn-on Delay Time
Rise Time Turn-off Delay Time
Fall Time
Qgd QSW
Qoss Rg td(on) tr td (off) tf
2.9 3.66 5.2
14 16.8 1.2 12 17 25 6
2.9 3.66
14 16.8 1.2 Ω 12 17 ns 25 6
VDS = 16V, VGS = 0
VDD = 16V ID = 7A Rg = 2Ω VRGeSs=ist4iv.5eVLoad
Source-Drain Rating & Characteristics
Parameter
Min Typ Max Min Typ Max Units
Conditions
Diode Forward Voltage*
VSD
1.2 1.2 V IS = 7A, VGS = 0V
Reverse Recovery Charge
Qrr
80
80
Reverse Recovery Charge (with Parallel
Qrr(s)
50
50
Schotkky)
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width ≤ 300 μs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board, t < 10 sec.
*
DTyepvi=cems eaarseu1re0d0%- Qteosssted to these parameters.
nC di/dt = 700A/μs VDS = 16V, VGS = 0V, IS = 7A
di/dt = 700A/μs (with 10BQ040) VDS = 16V, VGS = 0V, IS = 7A
2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback
October 16, 2014
IRF7807/ATRPbF-1
Power MOSFET Selection for DC/DC Converters
Control FET
Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses.
Power losses in the control switch Q1 are given by;
Ploss = P +conduction P +switching Pdrive+ Poutput
This can be expanded and approximated by;
( )Ploss =
I2 rms
×
Rds(on )
+
⎛ ⎜I ⎝
×
Qgd ig
× Vin
×
f ⎞⎟ ⎠
⎛ +⎜I
⎝
×
Qgs 2 ig
× Vin
×
f ⎞⎟ ⎠
( )+ Qg × Vg × f
+
⎛ ⎝
Qoss 2
× Vin
×
f
⎞ ⎠
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 1.
Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached (t1) and the time the drain current rises to Idmax (t2) at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure 2 shows how Qoss is formed by the parallel combination of the voltage dependant (non-linear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage.
t1 VGTH t0
Drain Current
4
t2 t3
1
Gate Voltage
2
Drain Voltage
QGS1 QGS2 QGD
Figure 1: Typical MOSFET switching waveform
Synchronous FET
The power loss equation for Q2 is approximated by;
Ploss
=
Pconduction
+
Pdrive
+
P* output
( )Ploss =
I2 rms
×
Rds(on)
( )+ Qg × Vg × f
( )+
⎛⎜ ⎝
Qoss 2
× Vin ×
f⎞ + ⎠
Qrr × Vin × f
*dissipated primarily in Q1.
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