Document
4Gb: x8, x16 DDR3L-RS SDRAM Description
DDR3L-RS SDRAM
EDJ4208EFBG-L – 64 Meg x 8 x 8 banks EDJ4216EFBG-L – 32 Meg x 16 x 8 banks
Description
The 1.35V DDR3L-RS SDRAM device is a low-voltage version of the DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V-compatible mode.
Features
• VDD = VDDQ = 1.35V (1.283–1.45V) • Backward compatible to VDD = VDDQ = 1.5V ±0.075V
– Supports DDR3L devices to be backward compatible in 1.5V applications
• Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • Programmable partial-array self refresh (PASR) • Reduced self refresh current
– IDD6: 2.2mA (TYP) at 25ºC
• TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C
• Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration
Options
• Configuration – 512 Meg x 8 – 256 Meg x 16
• FBGA package (Pb-free) – x8 – 78-ball (9mm x 10.6mm) Rev. F
• FBGA package (Pb-free) – x16 – 96-ball FBGA (9mm x 13.5mm) Rev. F
• Timing – cycle time – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333)
• Operating temperature – Commercial (0°C ≤ TC ≤ +95°C)1
• Revision: F
Note: 1. No guarantee on industrial and automotive temperature ranges.
Table 1: Key Timing Parameters
Speed Grade -GN2 -DJ1
Data Rate (MT/s) 1600 1333
Target tRCD-tRP-CL 11-11-11 9-9-9
Notes: 1. Backward compatible to 1066, CL = 7. 2. Backward compatible to 1333, CL = 9.
Table 2: Addressing
Parameter Configuration Refresh count
512 Meg x 8 64 Meg x 8 x 8 banks
8K
tRCD (ns) 13.75 13.5
tRP (ns) 13.75 13.5
CL (ns) 13.75 13.5
256 Meg x 16 32 Meg x 16 x 8 banks
8K
PDF: 09005aef859bddc0 4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing (Continued)
Parameter Row address Bank address Column address Page size
512 Meg x 8 64K (A[15:0])
8 (BA[2:0]) 1K (A[9:0])
1KB
4Gb: x8, x16 DDR3L-RS SDRAM Description
256 Meg x 16 32K (A[14:0])
8 (BA[2:0]) 1K (A[9:0])
2KB
Figure 1: DDR3L-RS Part Numbers
E D J 42 04 E F BG - GN L - F - D
Micron Technology (Micron Japan)
Type D = Packaged device
Product Family J = DDR3 SDRAM
Density/Bank 42 = 4Gb/8-bank
Organization 04 = x4 08 = x8 16 = x16
Packing Media D = Dry Pack (Tray) R = Tape and Reel
Environment Code F = Lead-free (RoHS-compliant)
an.