74AUP1G02

74AUP1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G02 is a single, two-input, positive NOR gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y = A + B or Y = A B Features Advanced Ultra Low Power (AUP) CMOS Supply Voltage Range from 0.8V to 3.6V ±4mA Output Drive at 3.0V Low Static Power Consumption ICC < 0.9µA Low Dynamic Power Consumption CPD = 6.4pF (Typical at 3.6V) Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250 mV at Vcc = 3.0V. IOFF Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101) Latch-Up Exceeds 100mA per JESD 78, Class I Leadless Packages Named per JESD30E Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) Applications Suited for Battery and Low Power Needs Wide array of products such as: Tablets, E-readers Cell Phones, Personal Navigation / GPS MP3 Pl...