Document
Preliminary
SH38300/SH38301
2.4GHz GFSK Transceiver
General Description
SH38300/38301 is a monolithic CMOS integrated circuit for wireless applications in 2.4GHz ISM band. The device is provided in a 32-lead plastic QFN5X5 packaging and is designed as a complete GFSK transceiver up to 3Mbps/ 1Mbps data rate. The chip features a fully programmable frequency synthesizer with integrated VCO circuitry.
Typical Applications
Wireless digital audio Wireless Mouse and Keyboard 2.4GHz ISM Band Communication System Wireless game pad Wireless toy
1/22 V1.2
Pin configuration
SH38300/SH38001
RSS I BP _DS BP _LPF SP I _CS SP I _CLK SP I _TXD SP I _RXD VDD _ D
32 31 30 29 28 27 26 25
BP_L I M2 BP _ L I M1
BP _BPF VDD_ A RF I RFO
VDD _ VCO BP _VCO
1 2 3 4 5 6 7 8
24 RX _CLK 23 RX _SYN 22 CD _TXEN 21 TRXD 20 TXD 19 F _CL K 18 RESTEN 17 MS0
VT 9 CPO 10 VDD_P L L 11
X I 12 XS 13 FP _RDY 14 BB _CL K 15 MS 1 16
SH38300/38301 QFN Package Top View
Important Notice:
Sinowealth reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. Sinowealth integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of Sinowealth products in such applications is understood to be fully at the risk of the customer.
2/22 V1.2
Block Diagram
SH38300/SH38001
RSS I BP _DS BP _L P F SP I _CS SP I _C LK SP I _TXD SP I_RXD VD D _D
32
BP _L IM2 1
BP _L IM1 2 BP _BPF 3
VDD_A 4 RFI 5
LNA
RFO 6 VDD_VCO 7
BP _VCO 8
PA VCO
9
31 30 29 28 27 26 25 SPI
RS S I
BPF LIMITER AGC
LPF DS 90
MOD
C RYS TAL OS C ILLATOR
PLL
System Control Logic
10 11 12 13 14 15 16
MODEM INTERFACE
24 RX _C LK 23 RX_SYN 22 CD_TXEN 21 TRXD 20 TXD 19 F _CLK
18 RE STEN 17 MS0
VT CPO VDD_PL L
XI XS F P _RDY BB_CLK MS1
System block diagram
3/22 V1.2
SH38300/SH38001
Specification (Ta=25℃, VDD=2.5V, data rate= 3Mbps, TX data without Gaussian shaping unless otherwise noted.)
Parameter General Operating Temperature Supply Voltage Current Consumption Transceiver Circuit
Phase Locked Loop X’TAL Settling Time X’TAL Frequency
VCO Operation Frequency PLL Settling Time @settle to 20KHz Transmitter TX Power Power Control Range In-band Spurious
Out-band Spurious 2 (Operating Mode)
Frequency Deviation
TX Settling Time Receiver Sensitivity @BER=0.001
IF Frequency
Image Rejection Maximum Input Power Spurious Emission 2
AGC Gain Control RSSI Range RSSI Slope Accuracy RX Settling Time
Description
RX Mode TX Mode @0dBm output TX Mode @-6dBm output
Synthesizer Mode Standby Mode Sleep Mode
@1M Mode 1 @3M Mode 1
@ Loop BW = 30 KHz
@ Maximum Power Setting
Adjacent Channel Second Channel ≧Third Channel
30MHz~1GHz 1GHz~12.75GHz 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz
@1M Mode @3M Mode @ Loop BW = 30 KHz
@1M Mode @3M Mode @1M Mode @3M Mode
@RF input 30MHz~1GHz 1GHz~12.75GHz
@RF input @RF input= -70 and –80 dBm
@ Loop BW =.