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NCP81148 Dataheets PDF



Part Number NCP81148
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Synchronous Buck Controller
Datasheet NCP81148 DatasheetNCP81148 Datasheet (PDF)

NCP81148 Advance Information Synchronous Buck Controller with Auto Power Saving Mode and Built-In LDO NCP81148 is a dual synchronous buck controller that is optimized for converting the battery voltage or adaptor voltage into multiple power rails required in desktop and notebook system. NCP81148 consists of two buck switching controllers with fixed 5.0 V output on channel 2, 3.3 V on channel 1 and two on−board LDOs with three outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81148 supports hig.

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NCP81148 Advance Information Synchronous Buck Controller with Auto Power Saving Mode and Built-In LDO NCP81148 is a dual synchronous buck controller that is optimized for converting the battery voltage or adaptor voltage into multiple power rails required in desktop and notebook system. NCP81148 consists of two buck switching controllers with fixed 5.0 V output on channel 2, 3.3 V on channel 1 and two on−board LDOs with three outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81148 supports high efficiency, fast transient response and provides power good signals. ON Semiconductor proprietary adaptive−ripple control enables seamless transition from CCM to DCM, where converter runs at reduced switching frequency with much higher efficiency at light load. The part operates with supply voltage ranging from 5.5 V to 28 V. NCP81148 is available in a 28−pin QFN package. Features • Wide Input Voltage Range: from 5.5 V to 28 V • Built−in 5 V / 60 mA LDO • Built−in selectable 3.3 V or 12 V / 10 mA LDO • Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz • 180 Interleaved Operation Between the Two Channels in Continue−Conduction−Mode (CCM) • Selected Power−Saving Mode/Forced PWM Mode • Transient−Response−Enhancement (TRE) Control • Input Supply Voltage Feed Forward Control • Resistive or Lossless Inductor’s DCR Current Sensing • Over−Temperature Protection • Internal Fixed 8.5 ms Soft−Start • Fixed Output Voltages 5 V and 3.3 V • Power Good Outputs for Both Channels • Built−in Adaptive Gate Drivers • Output Discharge Operation • Built−in Over−Voltage, Under−Voltage Protection • Accurate Over−Current Protection • Thermal Shutdown Applications • Desktop / Notebook Computers • System Power Supplies • I/O Power Supplies This document contains information on a new product. Specifications and information herein are subject to change without notice. http://onsemi.com MARKING DIAGRAM 1 28 PIN QFN, 4x4 MN SUFFIX CASE 485AR 81148 ALYWG G 81148 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS 5V_LDOBYP 5V_LDOOUT 5V_LDOEN SKIP LDO2_EN LDO2_OUT VIN GH2 BST2 SWN2 GL2 PGND2 CSP2 CSN2 28 1 GND GH1 BST1 SWN1 GL1/FSET PGND1 CSP1 CSN1 FB2 COMP2 EN2/SS2 PG EN1/SS1 COMP1 FB1 (Top View) ORDERING INFORMATION Device NCP81148MNTWG Package QFN−28 (Pb−Free) Shipping† 4,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 January, 2014 − Rev. P0 1 Publication Order Number: NCP81148/D VIN 5V_LDOEN ENABLE LDO VREF LDO2_EN ENABLE NCP81148 +− + − +− 5V_LDOOUT 5V_LDOBYP LDO2_OUT CSP1 CSN1 + CSA − COMP1 Vbias VREF FB1 SS + − E/A OC & TRE Detection EN1 PG GND PG1 PG2 Vbias VIN Control Logic Ramp Generator And PWM Logic UVLO, UVP, OVP, Power Good OCP, TSD and Protection SKIP BST1 GH1 SW1 5V_LDOOUT GL1/ FSET PGND1 Switcher 1 Shown Figure 1. Block Diagram http://onsemi.com 2 NCP81148 Table 1. PIN DESCRIPTIONS Pin No. Symbol Description 1, 21 GH1, GH2 Gate driver output of the top N−channel MOSFET. 2, 20 BST1, BST2 Top gate driver input supply, a bootstrap capacitor connection between SWNx and this pin. 3, 19 SWN1, SWN2 Switch node between the top MOSFET and bottom MOSFET. 4 GL2 Gate driver output of bottom N−channel MOSFET in channel2. 18 GL1/FSET Gate driver output of bottom N−channel MOSFET in channel1. And it is also used to set up switching frequency by connecting a resistor from this pin to ground. 5, 17 PGND1, PGND2 Power ground for channel 1 & 2. 6, 16 CSP1, CSP2 Inductor current differential sense non−inverting input. 7, 15 CSN1, CSN2 Inductor current differential sense inverting input. 8, 14 FB1, FB2 Output voltage feed back. 9, 13 COMP1, COMP2 Output of the error amplifier. 10, 12 EN1, EN2 Channel 1 and channel 2 enable pin. Short this pin to ground to disable the switcher channel. Pull this pin high to enable the switcher channel. 11 PG Power good indicator for both output voltages. Open−drain output. 22 VIN Battery or Adaptor input voltage 23 LDO2_OUT Second internal LDO output. A capacitor of minimum 1.0 mF is recommended to connect between this pin and ground. 24 LDO2_EN Enable for second internal LDO − Tie to VCC to setup LDO2 output at 12 V − Tie to 1/2VCC to setup LDO2 output at 3.3 V − Tie to ground to disable LDO 25 SKIP DCM programming pin: − Ground this pin to setup automatic CCM−DCM transfer with 33 KHz minimum switching frequency limitation; − Connect this pin to VCC to force CCM operation; − Leave this pin open to give automatic CCM−DCM transfer with 33 KHz minimum switching frequency for channel 1 but forced CCM for channel 2. 26 5V_LDOEN Enable for internal 5 V LDO. 27 5V_LDOOUT The output for internal 5 V LDO. A capacitor o.


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