Document
NCP81161
VR12.5 Compatible Synchronous Buck MOSFET Drivers
The NCP81161 is a high performance dual MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. It can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time.
Adaptive anti−cross−conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. Bidirectional EN pin can provide a fault signal to controller when the gate driver fault detect under OVP, UVLO occur. Also, an under−voltage lockout function guarantees the outputs are low when supply voltage is low.
Features
• Faster Rise and Fall Times • Adaptive Anti−Cross−Conduction Circuit • Integrated Bootstrap Diode • Pre OV function • ZCD Detect • Floating Top Driver Accommodates Boost Voltages of up to 35 V • Output Disable Control Turns Off Both MOSFETs • Under−voltage Lockout • Power Saving Operation Under Light Load Conditions • Direct Interface to NCP6151 and Other Compatible PWM
Controllers
• Thermally Enhanced Package • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Power Solutions for Desktop Systems
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DFN8 MN SUFFIX CASE 506AA
MARKING DIAGRAM
1 A4MG G
A4 = Specific Device Code M = Date Code G = Pb−Free Device
ORDERING INFORMATION
Device
Package
Shipping†
NCP81161MNTBG DFN8 3000 / Tape & Reel (Pb−Free)
NCP81161MNTWG DFN8 3000 / Tape & Reel (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 2
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Publication Order Number: NCP81161/D
VCC PWM
NCP81161
BST 1
DRVH
PWM EN
FLAG 9
SW GND
VCC
DRVL
(Top View) Figure 1. Pin Diagram
Logic
Anti−Cross Conduction
VCC
BST DRVH SW
DRVL
EN ZCD
UVLO
Detection
Fault
Pre−OV
Figure 2. Block Diagram
Table 1. Pin Descriptions
Pin No.
Symbol
1 BST
2 PWM
3 EN 4 VCC 5 DRVL 6 GND 7 SW 8 DRVH 9 FLAG
Description Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. Logic input. A logic high to enable the part and a logic low to disable the part. Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. Low side gate drive output. Connect to the gate of low side MOSFET. Bias and reference ground. All signals are referenced to this node (QFN Flag). Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. High side gate drive output. Connect to the gate of high side MOSFET. Thermal flag. There is no electrical connection to the IC. Connect to ground plane.
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12V_POWER
R1 1.02
TP4 PWM DRON
C5 1uF
NCP81161
R143
R164 C4 0.027uF
0.0 NCP81161TP3
0.0 BST HG
VREG_SW1_HG
PWM SW
VREG_SW1_OUT
EN GND
TP6 TP7
VCC LG
VREG_SW1_LG
PAD TP8
TP1
TP2 R142
Q1 NTMFS4821N
C1 4.7uF
C2 4.7uF
+ C3 CE9 4.7uF 390uF
0.0 TP5
L VCCP
Q9 Q10 NTMFS4851N NTMFS4851N
R3 2.2
235nH JP13_ETCH CSN11
C6 2700pF
JP14_ETCH CSP11
Figure 3. Application Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol VCC
Pin Name Main Supply Voltage Input
VMAX 15 V
VMIN −0.3 V
BST
Bootstrap Supply Voltage
35 V wrt/ GND
−0.3 V wrt/SW
40 V ≤ 50 ns wrt/ GND
15 V wrt/ SW
SW
Switching Node
35 V
−5 V
(Bootstrap Supply Return)
40 V ≤ 50 ns
−10 V (200 ns)
DRVH
High Side Driver Output
BST+0.3 V
−0.3 V wrt/SW −2 V (<200 ns) wrt/SW
DRVL
Low Side Driver Output
VCC+0.3 V
−0.3 V DC −5 V (<200 ns)
PWM
DRVH and DRVL Control Input
6.5 V
−0.3 V
EN
Enable Pin
6.5 V
−0.3 V
GND
Ground
0V 0V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise)
Symbol
Parameter
Value
RqJA TJ TA
TSTG MSL
Thermal Characteristic (Note 1) Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level
74 0 to 150 −10 to +125 −55 to +150
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* The maximum package power dissipation must be observed. 1. I in2 Cu, 1 oz thickness. 2. Operation at −40°C to −10°C guaranteed by design, not production tested.
Unit °C/W
°C °C °C
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NCP81161
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < +125°C; 4.5 V < VCC < 13.2 V,
4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)
Parameter
Test Conditions
Min. Typ. Ma.