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NB3N108K Dataheets PDF



Part Number NB3N108K
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 3.3V Differential 1:8 Fanout Clock Data Driver
Datasheet NB3N108K DatasheetNB3N108K Datasheet (PDF)

NB3N108K 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs Description The NB3N108K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N108K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, HCSL signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accep.

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NB3N108K 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs Description The NB3N108K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N108K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, HCSL signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility. Output drive current is set by connecting a 475 W resistor from IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS receivers when terminated per Figure 11. The NB3N108K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB3N108K’s performance to distribute low skew clocks across the backplane or the motherboard. Features • Typical Input Clock Frequency 100, 133, 166, or 400 MHz • 220 ps Typical Rise and Fall Times • 800 ps Typical Propagation Delay • Dtpd 100 ps Maximum Propagation Delay Variation Per Each Diff Pair • 0.1 ps Typical Integrated Phase Jitter RMS • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V • Differential HCSL Output Levels • LVDS Output Levels with Interface Termination • These are Pb−Free Devices Applications • Clock Distribution • PCIe I, II, III • Networking and Communications • High End Computing • Routers End Products • Servers • FBDIMM Memory Card • Ethernet Switch/Routers http://onsemi.com 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM* 1 NB3N 108K AWLYYWWG A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Q0 VTCLK Q0 Q1 Q1 CLK CLK VTCLK VCC GND IREF RREF Q6 Q6 Q7 Q7 Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2012 April, 2012 − Rev. 6 1 Publication Order Number: NB3N108K/D NB3N108K VCC Q0 Q0 Q1 Q1 Q2 Q2 VCC Exposed Pad (EP) 32 31 30 29 28 27 26 25 IREF 1 VTCLK 2 CLK 3 CLK 4 VTCLK 5 NC 6 NC 7 GND 8 NB3N108K 24 VCC 23 Q3 22 Q3 21 Q4 20 Q4 19 Q5 18 Q5 17 VCC 9 10 11 12 13 14 15 16 VCC NC NC Q7 Q7 Q6 Q6 VCC Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IREF Use the IREF pin to set the output drive. Connect a 475 W RREF resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies IREF by a factor of 5.4x to force 14 mA through a 50 W output load. See Figures 6 and 12. 2, 5 VTCLK, VTCLK − Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self−oscillation. 3 CLK LVPECL HCSL, LVDS Clock (TRUE) Input Input 4 CLK LVPECL HCSL, LVDS Clock (INVERT) Input Input 12, 14, 18, 20, 22, 26, 28, 30 Q[7−0]b HCSL or LVDS (Note 1) Output (INVERT) (Note 1) Output 13, 15, 19, 21, 23, 27, 29, 31 Q[7−0] HCSL or LVDS (Note 1) Output (TRUE) (Note 1) Output 6, 7, 10, 11 NC No Connect 8 GND − Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 9, 16, 17, 24, 25, 32 VCC − Positive Voltage Supply pin. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat−sinking conduit for proper thermal operation and electrically connected to the circuit board ground (GND). 1. Outputs can also interface to LVDS receiver when terminated per Figure 11. http://onsemi.com 2 NB3N108K Table 2. ATTRIBUTES Characteristic ESD Protection Human Body Model Machine Model Moisture Sensitivity (Note 2) QFN−52 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Value >2 kV 200 V Level 1 UL 94 V−0 @ 0.125 in 286 Table 3. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition 1 Condition 2 Rating Unit VCC VI IOUT Positive Power Supply Positive Input Output Current GND = 0 V GND = 0 V Continuous Surge 4.6 GND − 0.3 ≤ VI ≤ VCC 50 100 V V mA mA TA Operating Temperature Range QFN32 Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN32 QFN32 −40 to +85 −65 to +150 31 27 °C °C °C/W °C/W qJC Ther.


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