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74VHC125 Dataheets PDF



Part Number 74VHC125
Manufacturers NXP
Logo NXP
Description Quad buffer/line driver
Datasheet 74VHC125 Datasheet74VHC125 Datasheet (PDF)

74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 02 — 13 October 2009 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the o.

  74VHC125   74VHC125



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74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 02 — 13 October 2009 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2. Features I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC125 operates with CMOS logic levels N The 74VHCT125 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74VHC125D 74VHCT125D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74VHC125PW −40 °C to +125 °C 74VHCT125PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74VHC125BQ −40 °C to +125 °C 74VHCT125BQ DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 NXP Semiconductors 4. Functional diagram 74VHC125; 74VHCT125 Quad buffer/line driver; 3-state 2 1A 1Y 3 1 1OE 5 2A 2Y 6 4 2OE 9 3A 3Y 8 10 3OE 12 4A 4Y 11 13 4OE mna228 Fig 1. Logic symbol 21 1 EN1 5 4 3 6 9 8 10 12 11 13 mna229 Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning nA nY nOE mna227 Fig 3. Logic diagram (one buffer) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 74VHC125 74VHCT125 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y 001aak044 Fig 4. Pin configuration SO14 and TSSOP14 74VHC125 74VHCT125 1 1OE 14 VCC terminal 1 index area 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND(1) 13 4OE 12 4A 11 4Y 10 3OE 9 3A GND 7 3Y 8 001aak045 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration DHVQFN14 74VHC_VHCT125_2 Product data sheet Rev. 02 — 13 October 2009 © NXP B.V. 2009. All rights reserved. 2 of 15 NXP Semiconductors 74VHC125; 74VHCT125 Quad buffer/line driver; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 1A, 2A, 3A, 4A 2, 5, 9, 12 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 GND 7 VCC 14 6. Functional description Description output enable input (active LOW) data input data output ground (0 V) supply voltage Table 3. Control nOE L Function.


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