D-S MOSFET. B3910S Datasheet


B3910S MOSFET. Datasheet pdf. Equivalent


Part Number

B3910S

Description

N-Channel 30-V (D-S) MOSFET

Manufacture

BiTEK

Total Page 1 Pages
Datasheet
Download B3910S Datasheet


B3910S
N-Channel 30-V (D-S) MOSFET
B3910S
General Description
The B3910S is the N-Channel logic enhancement
mode power field effect transistors are produced
using high cell density, DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage application such
as cellular phone and notebook computer power
management and other battery powered circuits
where high-side switching and low in-line power
loss are needed in a very small outline surface
mount package.
Pin Configuration
SD
SD
SD
GD
Features
RDS(ON)=22m@VGS=10V
RDS(ON)=26m@VGS=4.5V
Super High Density Cell Design for
Extremely Low RDS(ON)
Exceptional On-Resistance and
Maximum DC Current
SOP-8 Package
Applications
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
Absolute Maximum Ratings (TA=25 Unless Otherwise Noted):
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(tJ=150 )
TA=25
TA=70
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
TA=25
Maximum Power Dissipation
TA=70
Operating Junction Temperature
Thermal Resistance-Junction to Case
Symbol
VDSS
VGSS
ID
IDM
IS
PD
TJ
RθJC
N-Channel
30
±25
9
7
30
1.7
2.0
1.44
-55 to 150
48
Unit
V
V
A
A
A
W
/W
Confidential material for authorized user only and BiTEK
reserves the utmost right upon the information contained herein.
3
www.BiTEK.com.tw


Features N-Channel 30-V (D-S) MOSFET B3910S Gen eral Description The B3910S is the N-Ch annel logic enhancement mode power fiel d effect transistors are produced using high cell density, DMOS trench technol ogy. This high density process is espec ially tailored to minimize on-state res istance. These devices are particularly suited for low voltage application suc h as cellular phone and notebook comput er power management and other battery p owered circuits where high-side switchi ng and low in-line power loss are neede d in a very small outline surface mount package. Pin Configuration SD SD SD GD Features RDS(ON)=22mΩ@VGS=10V RDS(O N)=26mΩ@VGS=4.5V Super High Density C ell Design for Extremely Low RDS(ON) Ex ceptional On-Resistance and Maximum DC Current SOP-8 Package Applications Powe r Management in Note book Portable Equi pment Battery Powered System DC/DC Conv erter Load Switch DSC ℃Absolute Maxi mum Ratings (TA=25 Unless Otherwise Not ed): Parameter Drain-Source Voltage Gate-Source Voltage ℃Continuou.
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