B4953 D-S MOSFET Datasheet

B4953 Datasheet, PDF, Equivalent


Part Number

B4953

Description

Dual P-Channel 30-V (D-S) MOSFET

Manufacture

BiTEK

Total Page 1 Pages
Datasheet
Download B4953 Datasheet


B4953
B4953
Dual P-Channel 30V (D-S) MOSFET
General Description
The B4953 is the Dual P-Channel logic
enhancement mode power field effect transistors
are produced using high cell density, DMOS trench
technology. This high density process is especially
tailored to minimize on-state resistance. These
devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery
powered circuits where high-side switching, and low
in-line power loss are needed in a very small outline
surface mount package.
Pin Configuration
Features
-30V/-5.3A, RDS(ON)=60m@VGS=-10V
-30V/-4.2A, RDS(ON)=90m@VGS=-4.5V
Super High Density Cell Design for
Extremely Low RDS(ON)
Exceptional On-Resistance and Maximum
DC Current Capability
SOP-8 Package
Applications
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
Absolute Maximum Ratings (TA=25 Unless Otherwise Noted):
Parameter
Symbol
Limit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(tJ=150 )
TA=25
TA=70
VDSS
VGSS
ID
-30
±20
-5.3
-4.3
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
TA=25
Maximum Power Dissipation
TA=70
IDM
IS
PD
-30
-1.7
2.0
1.3
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient*
Thermal Resistance-Junction to Case
TJ
Tstg
RθJA
RθJC
-55 to 150
-55 to 150
T 10 sec
Steady State
45
47
75
Unit
V
V
A
A
A
W
/W
/W
Confidential material for authorized user only and BiTEK
reserves the utmost right upon the information contained herein.
4
www.BiTEK.com.tw


Features B4953 Dual P-Channel 30V (D-S) MOSFET G eneral Description The B4953 is the Dua l P-Channel logic enhancement mode powe r field effect transistors are produced using high cell density, DMOS trench t echnology. This high density process is especially tailored to minimize on-sta te resistance. These devices are partic ularly suited for low voltage applicati on such as cellular phone and notebook computer power management and other bat tery powered circuits where high-side s witching, and low in-line power loss ar e needed in a very small outline surfac e mount package. Pin Configuration Fea tures -30V/-5.3A, RDS(ON)=60mΩ@VGS=-1 0V -30V/-4.2A, RDS(ON)=90mΩ@VGS=-4.5V Super High Density Cell Design for Ext remely Low RDS(ON) Exceptional On-Resis tance and Maximum DC Current Capability SOP-8 Package Applications Power Manag ement in Note book Portable Equipment B attery Powered System DC/DC Converter L oad Switch DSC LCD Display inverter Absolute Maximum Ratings (TA=25 Unless Otherwise Noted): Parameter .
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