EFFECT TRANSISTOR. NP20P06SLG Datasheet


NP20P06SLG TRANSISTOR. Datasheet pdf. Equivalent


NP20P06SLG


MOS FIELD EFFECT TRANSISTOR
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP20P06SLG

SWITCHING P-CHANNEL POWER MOSFET

DESCRIPTION The NP20P06SLG is P-channel MOS Field Effect Transistor designed for high current switching applications.

ORDERING INFORMATION

PART NUMBER NP20P06SLG-E1-AY Note NP20P06SLG-E2-AY Note

LEAD PLATING Pure Sn (Tin)

PACKING Tape 2500 p/reel

Note Pb-free (This product does not contain Pb in external electrode.)

PACKAGE TO-252 (MP-3ZK)

FEATURES • Super low on-state resistance
RDS(on)1 = 48 mΩ MAX. (VGS = −10 V, ID = −10 A) RDS(on)2 = 64 mΩ MAX. (VGS = −4.5 V, ID = −10 A) • Low input capacitance Ciss = 1650 pF TYP. • Built-in gate protection diode

(TO-252)

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage (VGS = 0 V)

VDSS

Gate to Source Voltage (VDS = 0 V)

VGSS

Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1

ID(DC) ID(pulse)

Total Power Dissipation (TC = 25°C)

PT1

Total Power Dissipation (TA = 25°C)

PT2

Channel Temperature

Tch

Storage Temperature Single Avalanche Current Note2 Single Avalanche Energy Note2

Tstg IAS EAS

−60 m20 m20 m60 38
1.2
175
−55 to +175 17
28

Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V

V V A A W W °C °C A mJ

THERMAL RESISTANCE Channel to Case Thermal Resistance Channel to Ambient Thermal Resistance

Rth(ch-C) Rth(ch-A)

3.9 125

°C/W °C/W

The information in this doc...



NP20P06SLG
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP20P06SLG
SWITCHING
P-CHANNEL POWER MOSFET
DESCRIPTION
The NP20P06SLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
NP20P06SLG-E1-AY Note
NP20P06SLG-E2-AY Note
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 2500 p/reel
Note Pb-free (This product does not contain Pb in external electrode.)
PACKAGE
TO-252 (MP-3ZK)
FEATURES
Super low on-state resistance
RDS(on)1 = 48 mΩ MAX. (VGS = 10 V, ID = 10 A)
RDS(on)2 = 64 mΩ MAX. (VGS = 4.5 V, ID = 10 A)
Low input capacitance
Ciss = 1650 pF TYP.
Built-in gate protection diode
(TO-252)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tstg
IAS
EAS
60
m20
m20
m60
38
1.2
175
55 to +175
17
28
Notes 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 0 V
V
V
A
A
W
W
°C
°C
A
mJ
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
3.9
125
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D19076EJ1V0DS00 (1st edition)
Date Published December 2007 NS
Printed in Japan
2007

NP20P06SLG
NP20P06SLG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 60 V, VGS = 0 V
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 10 V, ID = 10 A
VGS = 10 V, ID = 10 A
RDS(on)2
VGS = 4.5 V, ID = 10 A
Input Capacitance
Ciss VDS = 10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 30 V, ID = 10 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG VDD = 48 V,
Gate to Source Charge
QGS VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 20 A
IF = 20 A, VGS = 0 V
Reverse Recovery Time
trr IF = 20 A, VGS = 0 V,
Reverse Recovery Charge
Qrr di/dt = 100 A/μs
Note Pulsed test PW 350 μs, Duty Cycle 2%
MIN.
1.0
7
TYP.
1.6
14
36
42
1650
200
130
8
8
160
80
34
4
9
0.95
38
51
MAX.
10
m10
2.5
48
64
1.5
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 0 V
50 Ω
VDD
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS()
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS()
VGS
Wave Form
0 10%
VDS()
90%
VDS
VDS
Wave Form 0
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D19076EJ1V0DS




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)