EFFECT TRANSISTOR. NP32N055IDE Datasheet


NP32N055IDE TRANSISTOR. Datasheet pdf. Equivalent


NP32N055IDE


MOS FIELD EFFECT TRANSISTOR
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP32N055HDE, NP32N055IDE, NP32N055SDE

SWITCHING N-CHANNEL POWER MOSFET

DESCRIPTION
These products are N-channel MOS Field Effect Transistor designed for high current switching applications.
FEATURES
• Channel temperature 175 degree rated • Super low on-state resistance
RDS(on)1 = 24 mΩ MAX. (VGS = 10 V, ID = 16 A) RDS(on)2 = 29 mΩ MAX. (VGS = 5.0 V, ID = 16 A) • Low Ciss : Ciss = 1300 pF TYP.

ORDERING INFORMATION

PART NUMBER

PACKAGE

NP32N055HDE NP32N055IDE Note

TO-251 (JEITA) / MP-3 TO-252 (JEITA) / MP-3Z

NP32N055SDE
Note Not for new design.

TO-252 (JEDEC) / MP-3ZK

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage (VGS = 0 V)

VDSS

55

Gate to Source Voltage (VDS = 0 V)

VGSS

±20

Drain Current (DC) (TC = 25°C)

ID(DC)

±32

Drain Current (pulse) Note1

ID(pulse)

±100

Total Power Dissipation (TC = 25°C)

PT1

66

Total Power Dissipation (TA = 25°C)

PT2

1.2

Channel Temperature

Tch 175

Storage Temperature

Tstg –55 to +175

Single Avalanche Current Note2

IAS 28 / 21 / 8

Single Avalanche Energy Note2

EAS 7.8 / 44 / 64

V V A A W W °C °C A mJ

(TO-251) (TO-252)

Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Starting Tch = 25°C, RG = 25 Ω , VGS = 20 → 0 V

THERMAL RESISTANCE
Channel to Case Thermal Resistance Channel to Ambient Thermal Resistance

Rth(ch-C) Rth(ch-A)

2.27 °C/W 125 °C/W

The information in this docum...



NP32N055IDE
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP32N055HDE, NP32N055IDE, NP32N055SDE
SWITCHING
N-CHANNEL POWER MOSFET
DESCRIPTION
These products are N-channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
Channel temperature 175 degree rated
Super low on-state resistance
RDS(on)1 = 24 mMAX. (VGS = 10 V, ID = 16 A)
RDS(on)2 = 29 mMAX. (VGS = 5.0 V, ID = 16 A)
Low Ciss : Ciss = 1300 pF TYP.
ORDERING INFORMATION
PART NUMBER
PACKAGE
NP32N055HDE
NP32N055IDE Note
TO-251 (JEITA) / MP-3
TO-252 (JEITA) / MP-3Z
NP32N055SDE
Note Not for new design.
TO-252 (JEDEC) / MP-3ZK
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
55
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
Drain Current (DC) (TC = 25°C)
ID(DC)
±32
Drain Current (pulse) Note1
ID(pulse)
±100
Total Power Dissipation (TC = 25°C)
PT1
66
Total Power Dissipation (TA = 25°C)
PT2
1.2
Channel Temperature
Tch 175
Storage Temperature
Tstg –55 to +175
Single Avalanche Current Note2
IAS 28 / 21 / 8
Single Avalanche Energy Note2
EAS 7.8 / 44 / 64
V
V
A
A
W
W
°C
°C
A
mJ
(TO-251)
(TO-252)
Notes 1. PW 10 µs, Duty Cycle 1%
2. Starting Tch = 25°C, RG = 25 , VGS = 20 0 V
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
2.27 °C/W
125 °C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D15309EJ2V0DS00 (2nd edition)
Date Published July 2005 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001, 2005

NP32N055IDE
NP32N055HDE, NP32N055IDE, NP32N055SDE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 55 V, VGS = 0 V
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
IGSS
VGS(th)
| yfs |
RDS(on)1
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 16 A
VGS = 10 V, ID = 16 A
RDS(on)2 VGS = 5.0 V, ID = 16 A
RDS(on)3 VGS = 4.5 V, ID = 16 A
Input Capacitance
Ciss VDS = 25 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 28 V, ID = 16 A
Rise Time
Turn-off Delay Time
tr
td(off)
VGS = 10 V
RG = 1
Fall Time
tf
Total Gate Charge
QG1 VDD = 44 V, VGS = 10 V, ID = 32 A
QG2 VDD = 44 V
Gate to Source Charge
QGS VGS = 5.0 V
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 32 A
IF = 32 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr IF = 32 A, VGS = 0 V
Qrr di/dt = 100 A/µs
Note Pulsed
MIN. TYP. MAX. UNIT
10 µA
±100 nA
1.5 2 2.5 V
8 16
S
19 24 m
22 29 m
24 33 m
1300 2000 pF
180 270 pF
90 160 pF
14 31 ns
8 20 ns
40 81 ns
7.4 19 ns
27 41 nC
15 23 nC
5 nC
9 nC
1.0 V
41 ns
58 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25
PG.
VGS = 20 0 V
50
L
VDD
ID
VDD
IAS
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG. RG
VGS
0
τ
τ = 1 µs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
90%
VGS
90%
10% 10%
tr td(off)
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50
RL
VDD
2 Data Sheet D15309EJ2V0DS




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