Document
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller
AP386X
General Description
The AP386X is a low-cost high-resolution single chip solution for APA (All point addressable) capacitive touch screen. It is an 8-bit single cycle 8051 microcontroller with ICP Interface. The chip includes 12-bit successive approximation analog-to-digital converters with an I2C interface and multiplexer-switcher circuits for flexible measurement of analog signal from APA panel. An accurate switched-capacitor integrator is built-in and it can auto calibrate the pixel parameters for a wide range of capacitance on the touch screen (1pF to 32pF). This touch screen controller (TSC) with CMOS integration circuit provides an ideal choice for APA touch panel. The AP386X is specified over the temperature range of -40°C to 85°C.
The AP386X is available in QFN-5×5-40 (for AP3860) and QFN-6×6-48 (for AP3861) packages.
Features
• Mutual Capacitive Touch Sensing • Single Power Supply: 2.8V to 3.6V Operation
Voltage; LDO inside to Support 1.6V to 2.0V Operation Voltage • Up to 17/23 Drive Lines and 10/12 Sense Lines • Charge Pump Support up to 6V, Doubling SNR • Internal Two-wire Serial Control Bus I2C • Single-end Integrator with Programmable Gain Control • Multiplexed Analog Digitization with 12-bit Resolution Scan SAR ADCs and Its Dedicated 2X to 8X Accumulator XSRAM Buffers
Features (Continued)
• Single Cycle 8051 CPU Core, Maximum Operating Clock up to 28MHz from IOSC (Zero Wait State) 4 to 28MHz Internal Oscillator (IOSC) 32k-byte Flash ROM 6k-byte Internal SRAM Two 16-bit Timers T0/T1 Configurable I2C Slave Controller and SPI Slave Controller Shared with the Same Ports With Asynchronous I2C Slave Address Detection Logic Design 4 General Purpose GPIO Pins One External Interrupt Pin
• ISP/IAP via I²C Port • Operation Temperature Range: -40°C to 85°C • Package Type Alternatives: QFN-5×5-40 and
QFN-6×6-48 • RoHS Compliance • Operating Mode:
Mode Power-down Idle
Standard
Description No scan with power-down mode While only 8051 CPU core is idle, all peripherals remain active Higher scan rate when fingers are on panel, IOSC can up to 4MHz to 28MHz
Applications
• Mobile Phones • Personal Digital Assistants • Smart Hand-held or Gaming Devices
Aug. 2013 Rev. 1. 0
QFN-5×5-40
QFN-6×6-48
Figure 1. Package Types of AP386X BCD Semiconductor Manufacturing Limited
1
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller
AP386X
Pin Configuration
FN Package (QFN-5×5-40)
S1 S2 S3 S4 S5 S6 S7 S8 S9 D16
Pin 1 Mark
40 39 38 37 36 35 34 33 32 31
D15 1 D14 2 D13 3 D12 4 D11 5 D10 6 D9 7 D8 8 D7 9 D6 10
30 VDD3V 29 S0 28 INT/GPIO1 27 WAKE/GPIO0 26 RSTN 25 MISO/GPIO2 24 MOSI/SDA 23 SCK/GPIO3
41 22 SS/SCL
21 TESTEN
11 12 13 14 15 16 17 18 19 20
D5 D4 D3 D2 D1 D0 VDDHV VDD3V VSS VDD18
Figure 2. Pin Configuration of AP3860 (Top View)
Aug. 2013 Rev. 1. 0
BCD Semiconductor Manufacturing Limited 2
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller
AP386X
Pin Configuration (Continued)
FN Package (QFN-6×6-48)
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 D22
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VDDHV VDD3V
Figure 3. Pin Configuration of AP3861 (Top View)
Aug. 2013 Rev. 1. 0
BCD Semiconductor Manufacturing Limited 3
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller
AP386X
Pin Description
Pin Number
QFN-5×5-40 QFN-6×6-48
AP3860
AP3861
Pin Name
40, 1 to 16
6 to 22
D16 to D0
-
48, 1 to 5
D22 to D17
17 23 VDDHV
18, 30 19 20
24, 35 25 26
VDD3V VSS
VDD18
21 27 TESTEN
22 28 SS/SCL
23
29
SCK/ GPIO3
24
30
MOSI/ SDA
25
31
MISO/ GPIO2
Pin Type I/O, A I/O, A
O P P O I
I/O
I/O
I/O
I/O
Pin Function
Driving Lines 16 to 0 These pins can also be configured as I/O bi-directional ports for test
Driving Lines 22 to 17 These pins can also be configured as I/O bi-directional ports for test
High Voltage. 6V Charge pump high Voltage. This output pin can be configured as VDD3V or 6V accordingly
Supply Voltage. 2.8V to 3.6V A good decoupling capacitor between VDD3V and VSS pins is critical for good performance
Ground Voltage. 0V
Internal Regulator Output. 1.6V to 2.0V Typical decoupling capacitors of 0.1F and 10F should be connected between VDD18 and VSS
Test Mode Enable High Active This pin has an internal weakly pull low resistor connected. If it is connected high, the chip enters into Test Mode condition
SS/SCL This pin can be configured as the SCL signal of the I2C master or I2C slave controller. When I2C is enabled, the pin is configured as an open-collector. While in SPI mode, this pin is configured as the slave chip select pin
Port 1.3 GPIO 8051 P1.3 GPIO. This pin can also be configured as the serial clock from SPI master while SPI interface is activated
SDA This pin can be configured as the SDA signal of the I2C master or I2C slave controller. In this operation mode, this pin should also be configured as open-collector. While SPI int.