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74LVX373 Dataheets PDF



Part Number 74LVX373
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
Datasheet 74LVX373 Datasheet74LVX373 Datasheet (PDF)

74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS s HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V s 5V TOLERANT INPUTS s POWER-DOWN PROTECTION ON INPUTS s INPUT VOLTAGE LEVEL: )VIL = 0.8V, VIH = 2V at VCC =3V t(ss LOW POWER DISSIPATION: cICC = 4 µA (MAX.) at TA=25°C us LOW NOISE: dVOLP = 0.3V (TYP.) at VCC =3.3V ros SYMMETRICAL OUTPUT IMPEDANCE: P|IOH| = IOL = 4 mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tetPLH ≅ tPHL les OPERATING VOLTAGE RANGE: oV.

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74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS s HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V s 5V TOLERANT INPUTS s POWER-DOWN PROTECTION ON INPUTS s INPUT VOLTAGE LEVEL: )VIL = 0.8V, VIH = 2V at VCC =3V t(ss LOW POWER DISSIPATION: cICC = 4 µA (MAX.) at TA=25°C us LOW NOISE: dVOLP = 0.3V (TYP.) at VCC =3.3V ros SYMMETRICAL OUTPUT IMPEDANCE: P|IOH| = IOL = 4 mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tetPLH ≅ tPHL les OPERATING VOLTAGE RANGE: oVCC(OPR) = 2V to 3.6V (1.2V Data Retention) bss PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 - Os IMPROVED LATCH-UP IMMUNITY t(s)DESCRIPTION The 74LVX373 is a low voltage CMOS OCTAL cD-TYPE LATCH with 3 STATE OUTPUT NON duINVERTING fabricated with sub-micron silicon rogate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery Poperated and low noise 3.3V applications. teThis 8 bit D-Type latch is controlled by a latch leenable input (LE) and an output enable input (OE). oWhile the LE input is held at a high level, the Q soutputs will follow the data input precisely. SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX373MTR 74LVX373TTR When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ObFigure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 4 1/13 74LVX373 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION 1 OE 3 State Output Enable Input (Active LOW) 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 2, 5, 6, 9, 12, Q0 to Q7 3-State Outputs 15, 16,19 11 LE Latch Enable Input 10 GND Ground (0V) 20 VCC Positive Supply Voltage t(s)Table 3: Truth Table ucINPUTS rodOE LE HX PL L teL H leL H soX : Don’t Care bZ : High Impedance * : Q Outputs are Latched at the time when the LE INPUT is taken low logic level Obsolete Product(s) - OFigure 3: Logic Diagram D X X L H OUTPUT Q Z NO CHANGE* L H This logic diagram has not be used to estimate propagation delays 2/13 74LVX373 Table 4: Absolute Maximum Ratings Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC VCC or Ground Current ± 50 mA Tstg Storage Temperature )TL Lead Temperature (10 sec) -65 to +150 300 °C °C t(sAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied ucTable 5: Recommended Operating Conditions rodSymbol PVCC teVI leVO soTop bdt/dv Parameter Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 2) (VCC = 3V) O1) Truth Table guaranteed: 1.2V to 3.6V -2) VIN from 0.8V to 2.0V t(s)Table 6: DC Specifications Value 2 to 3.6 0 to 5.5 0 to VCC -55 to 125 0 to 100 Unit V V V °C ns/V ducSymbol Parameter te ProVIH High Level Input Voltage soleVIL Low Level Input ObVoltage Test Condition VCC (V) 2.0 3.0 3.6 2.0 3.0 3.6 Value TA = 25°C -40 to 85°C -55 to 125°C Unit Min. 1.5 2.0 2.4 Typ. Max. 0.5 0.8 0.8 Min. Max. 1.5 2.0 2.4 0.5 0.8 0.8 Min. 1.5 2.0 2.4 Max. 0.5 0.8 0.8 V V VOH High Level Output 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 Voltage 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 V 3.0 IO=-4 mA 2.58 2.48 2.4 VOL Low Level Output Voltage 2.0 IO=50 µA 3.0 IO=50 µA 0.0 0.1 0.1 0.1 0.0 0.1 0.1 0.1 V 3.0 IO=4 mA 0.36 0.44 0.55 IOZ High Impedance Output Leakage Current 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 5 µA II Input Leakage Current 3.6 VI = 5V or GND ± 0.1 ±1 ± 1 µA ICC Quiescent Supply Current 3.6 VI = VCC or GND 4 40 40 µA 3/13 74LVX373 Table 7: Dynamic Switching Characteristics Test Condition Value Symbol Parameter VCC (V) TA = 25°C -40 to 85°C -55 to 125°C Unit Min. Typ. Max. Min. Max. Min. Max. VOLP VOLV Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 0.3 0.8 -0.8 -0.3 Dynamic High VIHD Voltage Input (note 1, 3) 3.3 CL = 50 pF 2.0 V t(s)VILD Dynamic Low Voltage Input (note 1, 3) 3.3 0.8 1) Worst case package. c2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. u3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switc.


IXFV22N60PS 74LVX373 G9661


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