74LVX373

74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS s HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V s 5V TOLERANT INPUTS s POWER-DOWN PROTECTION ON INPUTS s INPUT VOLTAGE LEVEL: )VIL = 0.8V, VIH = 2V at VCC =3V t(ss LOW POWER DISSIPATION: cICC = 4 µA (MAX.) at TA=25°C us LOW NOISE: dVOLP = 0.3V (TYP.) at VCC =3.3V ros SYMMETRICAL OUTPUT IMPEDANCE: P|IOH| = IOL = 4 mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tetPLH ≅ tPHL les OPERATING VOLTAGE RANGE: oVCC(OPR) = 2V to 3.6V (1.2V Data Retention) bss PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 - Os IMPROVED LATCH-UP IMMUNITY t(s)DESCRIPTION The 74LVX373 is a low voltage CMOS OCTAL cD-TYPE LATCH with 3 STATE OUTPUT NON duINVERTING fabricated with sub-micron silicon rogate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery Poperated and low noise 3.3V applications. teThis 8 bit D-Type latch is controlled by a latch leenable input (LE) and an output enable input (OE). oWhile the LE input is held at a high level, the Q soutputs will follow the data input precisely. SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX373MTR 74LVX373TTR When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inp...