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MT90810AK3 Dataheets PDF



Part Number MT90810AK3
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description Flexible MVIP Interface Circuit
Datasheet MT90810AK3 DatasheetMT90810AK3 Datasheet (PDF)

CMOS MT90810 Flexible MVIP Interface Circuit Data Sheet Features • MVIP and ST-BUS compliant • MVIP Enhanced Switching with 384x384 channel capacity (256 MVIP channels; 128 local channels) • On-chip PLL for MVIP master/slave operation • Local output clocks of 2.048,4.096,8.192 MHz with programmable polarity • Local serial interface is programmable to 2.048, 4.096 or 8.192 Mb/s with associated clock outputs • Additional control output stream • Per-channel message mode • Two independently prog.

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CMOS MT90810 Flexible MVIP Interface Circuit Data Sheet Features • MVIP and ST-BUS compliant • MVIP Enhanced Switching with 384x384 channel capacity (256 MVIP channels; 128 local channels) • On-chip PLL for MVIP master/slave operation • Local output clocks of 2.048,4.096,8.192 MHz with programmable polarity • Local serial interface is programmable to 2.048, 4.096 or 8.192 Mb/s with associated clock outputs • Additional control output stream • Per-channel message mode • Two independently programmable groups of up to 12 framing signals each • Motorola non-multiplexed or Intel multiplexed/non-multiplexed microprocessor interface Applications • Medium size digital switch matrices • MVIP interface functions • Serial bus control and monitoring August 2005 Ordering Information MT90810AK3 100 Pin PQFP* *Pb Free Sn-Bi Plating Trays 0°C to +70°C • Centralized voice processing systems • Voice/Data multiplexer Description Zarlink’s MT90810 is a Flexible MVIP Interface Circuit (FMIC). The MVIP (Multi-Vendor Integration Protocol) compliant device provides a complete MVIP compliant interface between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. A built-in digital time-slot switch provides MVIP enhanced switching between the full MVIP Bus and any combination of up to 128 full duplex local channels of 64 kbps each. An 8 bit microprocessor port allows realtime control of switching and programming of device configuration. On-board clock circuitry, including both analog and digital phase-locked loops, supports all MVIP clock modes. The local interface supports PCM rates of 2.048, 4.096 and 8.192 Mb/s, as well as parallel DMA through the microprocessor port. SEC8K C4b C2o F0b DSo[0:7] DSi[0:7] LDO[0:3] LDI[0:3] TCK TMS TDI TDO EX_8KA EX_8KB X2 X1/CLKIN PLL_LO PLL_LI FRAME Timing and Clock Control (Oscillator and Analog & Digital PLLs) Enhanced Switch S-P/ Data Memory P-S Connection Memory Programmable Framing Signals JTAG Microprocessor Interface CLK2 CLK4 CLK8 RESET CSTo FGA[0:11] FGB[0:11] ERR AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1] R/W DS DTACK Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT90810 Data Sheet LDO0 VSS DSi7 DSo7 FGB9 DSi6 DSo6 DSi5 DSo5 DSi4 DSo4 FGA9 DSi3 DSo3 VSS VDD DSi2 DSo2 FGB8 DSi1 DSo1 DSi0 DSo0 FGA8 C4b F0b C2o SEC8K VSS FGB7 FGA10 LDO1 LDO2 FGB10 LDO3 VDD LDI0 LDI1 LDI2 LDI3 EX8_KA EX8_KB VSS FRAME CLK8 FGA11 CLK4 CLK2 FGB11 FGA0 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 82 48 84 46 86 44 88 42 90 92 100 PIN PQFP 40 38 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 DREQ1 DREQ0 DACK1 DACK0 FGA7 AD7 AD6 AD5 AD4 VSS VDD FGB6 AD3 AD2 AD1 AD0 A1 FGA6 A0 ERR FGA1 FGA2 FGA3 CSTo FGA4 FGB0 FGB1 FGB2 FGB3 TCK TDI TDO TMS FGB4 VDD VSS X1/CLKIN X2 RESET FGA5 VCO_VSS PLL_LO PLL_LI VCO_VDD WR/[R/W] RD/[DS] CS FGB5 ALE RDY/[DTACK] Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. MT90810 Data Sheet Pin Description Pin # 58, 60, 63, 67, 70, 72, 74, 77 59, 61, 64, 68, 71, 73, 75, 78 80, 82, 83, 85 87, 88, 89, 90 4 55 56 54 53 91 92 94 95 97 98 100, 1, 2, 3, 5, 20, 33, 46, 57, 69, 81, 96 6, 7, 8, 9, 14, 28, 39, 51, 62, 76, 84, 99 Name DSo[0:7] Description MVIP DSo Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming to ST-BUS serial data stream specifications. DSi[0:7] MVIP DSi Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming to ST-BUS serial data stream specifications. LDO[0:3] LDI[0:3] CSTo F0b C4b C2o SEC8K EX_8KA EX_8KB FRAME CLK8 CLK4 CLK2 FGA[0:11] Local Output Serial Streams (Output). Serial data streams programmable to 2.048, 4.096 or 8.192 Mb/s data rates. Local Input Serial Streams (TTL Input). Serial data streams programmable to 2.048, 4.096 or 8.192 Mb/s data rates. Control ST-BUS Output (Output). This is a 1.024 Mb/s output. The state of each bit in this stream is determined by the CSTo bit in connection memory high. MVIP F0 signal (CMOS Input/Output). ST-BUS 8 kHz framing signal MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096 MHz clock MVIP C2 signal (Output). ST-BUS 2.048 MHz clock. This pin is automatically set to high impedance when it is not driven. MVIP SEC8K signal (CMOS Input/Output). A secondary 8 kHz signal used either as an input source to the on-chip digital PLL or as an output to the MVIP bus. External 8 kHz input A (TTL Input). External 8 kHz input B (TTL Input). Local Frame Output Signal (Output). This 8 kHz framing signal has a duty cycle and period equal to the MVIP F0 signal. 8 MHz Local Output Clock (Output). This is a 8 MHz clock. 4 MHz Local Output Clock (Output). This 4 MHz clock has a duty cycle and period equal to the MVIP C4 signal. 2 MHz Local Output Clock (Output). This 2 MHz clock has a duty cycle and period equal t.


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