Document
A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM
256Mb Synchronous DRAM Specification
A3V56S30FTP A3V56S40FTP
Zentel Electronics Corp.
Revision 1.1
Mar., 2010
A3V56S30FTP
A3V56S40FTP 256M Single Data Rate Synchronous DRAM
General Description
A3V56S30FTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40FTP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. A3V56S30FTP and A3V56S40FTP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply - Maximum clock frequency : - 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQM (A3V56S30FTP), DQML and DQMU (A3V56S40FTP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Support concurrent auto-precharge - Auto and self refresh - 8192 refresh cycles /64ms - LVTTL Interface - Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch Pb-free package is available
Ordering Information
54Pin TSOPII (400mil x 875mil)
Part No.
Max. Frequency
A3V56S30FTP-G6 166MHz (CL=3)
A3V56S30FTP-G7 143MHz (CL=3)
A3V56S30FTP-G75 133MHz (CL=3)
A3V56S40FTP-G6 166MHz (CL=3)
A3V56S40FTP-G7 143MHz (CL=3)
A3V56S40FTP-G75 133MHz (CL=3)
Supply Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Zentel Electronics reserves the right to change products or specification without notice.
Revision 1.1
Page 1 / 39
Mar., 2010
A3V56S30FTP
A3V56S40FTP 256M Single Data Rate Synchronous DRAM
PIN CONFIGURATION (TOP VIEW) x8 x16
Vdd
DQ0 VddQ
NC
DQ1 VssQ NC
DQ2 VddQ NC
DQ3
VssQ NC
Vdd NC
/WE
/CAS /RAS /CS
BA0 BA1 A10(AP)
A0
A1 A2
A3 Vdd
Vdd
DQ0 VddQ
DQ1
DQ2 VssQ DQ3
DQ4 VddQ DQ5
DQ6
VssQ DQ7
Vdd DQML
/WE
/CAS /RAS /CS
BA0 BA1 A10(AP)
A0
A1 A2
A3 Vdd
PIN CONFIGURATION
(TOP VIEW)
1 54 2 53 3 52 4 51 5 50 6 49 7 48
8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36
20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28
Vss
DQ15 VssQ
DQ14
DQ13 VddQ DQ12
DQ11 VssQ DQ10
DQ9
VddQ DQ8
Vss
NC DQMU
CLK CKE A12
A11 A9 A8
A7
A6 A5
A4 Vss
Vss
DQ7 VssQ
NC
DQ6 VddQ NC
DQ5 VssQ NC
DQ4
VddQ NC
Vss
NC DQM
CLK CKE A12
A11 A9 A8
A7
A6 A5
A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-7 DQ0-15
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O (A3V56S30FTP) : Data I/O (A3V56S40FTP)
DQM : Output Disable / Write Mask (A3V56S30FTP) DQMU,L : Output Disable / Write Mask (A3V56S40FTP) A0-12 : Address Input BA0,1 : Bank Address Vdd : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output
Revision 1.1
Page 2 / 39
Mar., 2010
A3V56S30FTP
A3V56S40FTP 256M Single Data Rate Synchronous DRAM
Note:This figure shows the A3V56S30FTP The A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15
Type Designation Code A 3V 56 S40F TP-G6
Speed Grade
G: Green
75: 133MHz@CL=3 7: 143MHz@CL=3 6: 166MHz@CL=3
Package Type TP:TSOP (II)
Process Generation Function Reserved for Future Use Organization 2n 3:x8, 4:x16
SDR Synchronous DRAM Density 56:256M bits Interface V:LVTTL
Memory Style (DRAM) Zentel DRAM
Revision 1.1
Page 3 / 39
Mar., 2010
A3V56S30FTP
A3V56S40FTP 256M Single Data Rate Synchronous DRAM
Pin Descriptions
SYMBOL CLK
CKE
TYPE Input
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst / access in progress). CKE is synchronous except after the device enters self refresh mode, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
/CS
Input
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code.
/CAS, /RAS, /WE
DQM, DQML, DQMU,
Input Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in .