A3R1GE40JBF

A3R1GE30JBF A3R1GE40JBF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE30JBF A3R1GE40JBF Zentel Electronics Corp. Revision 1.0 Dec., 2014 A3R1GE30JBF A3R1GE40JBF 1Gb DDRII Synchronous DRAM Specifications Features Density: 1G bits Organization − 16M words × 8 bits × 8 banks (A3R1GE30JBF) − 8M words × 16 bits × 8 banks (A3R1GE40JBF) Package − 60-ball FBGA(μBGA) (A3R1GE30JBF) − 84-ball FBGA(μBGA) (A3R1GE40JBF) − Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 1.8V ± 0.1V Data rate: 1066Mbps/800Mbps (max.) 1KB page size (A3R1GE30JBF) − Row address: A0 to A13 − Column address: A0 to A9 2KB page size (A3R1GE40JBF) − Row address: A0 to A12 − Column address: A0 to A9 Eight internal banks for concurrent operation Interface: SSTL_18 Burst lengths (BL): 4, 8 Burst type (BT): − Sequential (4, 8) − Interleave (4, 8) /CAS Latency (CL): 3, 4, 5, 6, 7 Recharge: auto recharge option for each burst access Driver strength: normal/weak Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms − Average refresh period 7.8μs at TC≦ +85°C 3.9μs at TC＞ +85°C Industrial grade compliant with AEC-Q100 grade3 Automotive grade compliant with AEC-Q100 grade2 Operating case temperature range − TC = 0°C to +95°C (Commercial grade)* − TC = -40°C to +95°C (Industrial grade)* − TC = -40°C to +105°C (Automotive grade)* Double-data-rate architecture; two data transfers per clock cycle The high-speed data transfer is realized by the...