IDTVP386

8/28-BIT LVDS RECEIVER FOR VIDEO DATASHEET ADVANCE INFORMATION IDTVP386 General Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps throughput or 350 Mbytes per second. This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals. Features Wide clock frequency range from 20 MHz to 100 MHz Pin compatible with the National DS90CF386, THine THC63LVDF84, TISN65LVDS94 Converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data Fully spread spectrum compatible LVDS voltage swing of 350 mV for low EMI On-chip PLL requires no external components Low-power CMOS design Falling edge clock triggered outputs Power-down control function Compatible with TIA/EIA-644 LVDS standards Packaged in a 56-pin TSSOP (Pb free available) RxOUT0...27 Block Diagram RxIN0+ RxIN0RxIN1+ RxIN1RxIN2+ RxIN2RxIN3+ RxIN3- RxCLKIN+ RxCLKIN- PWRDWN LVDS to TTL De-serializer PLL 8 RED 8 GREEN 8 BLUE HSYNC VSYNC DATA ENABLE CONTROL RxCLKOUT VP386 8/28-BIT LVDS RECEIVER FOR VIDEO 1 IDTVP386 7129/3 IDTVP386 8/28-BIT LVDS RECEIVER FOR VIDEO Pin Assignment COMMERCIAL TEMPERATURE RANGE RxOUT22 RxOUT23 RxOUT24 GND RxOUT25 RxOUT26 RxOUT27 LVDS_GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS_VCC LVDS_GND RxIN2RxIN2+ RxCLKINRxICLKN+ RxIN3RxIN3+ LVDS_GND PLL_GND PLL_VCC PLL_GND PWRDWN RxCLKOUT RxOUT0 GN...