CY2302

Features ■ 90 ps typical jitter OUT2 ■ 200 ps typical jitter OUT1 ■ 65 ps typical output-to-output skew ■ 90 ps typical propagation delay ■ Voltage range: 3.3 V±5%, or 5 V±10% ■ Output frequency range: 5 MHz to 133 MHz ■ Two outputs ■ Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs ■ Available in 8-pin SOIC package CY2302 Frequency Multiplier and Zero Delay Buffer Table 1. Configuration Options FBIN OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 FS0 FS1 OUT1 0 0 2 X REF 1 0 4 X REF 01 REF 1 1 8 X REF 0 0 4 X REF 1 0 8 X REF 0 1 2 X REF 1 1 16 X REF OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF Logic Block Diagram FBIN External feedback connection to OUT1 or OUT2, not both FS0 FS1 ÷Q IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Cypress Semiconductor Corporation 198 Champion Court Document #: 38-07154 Rev. *E San Jose, CA 95134-1709 408-943-2600 Revised March 24, 2011 [+] Feedback CY2302 Pinouts Figure 1. Pin Configuration – 8-Pin SOIC Package FBIN IN GND FS0 1 2 3 4 8 OUT2 7 VDD 6 OUT1 5 FS1 Table 2. Pin Definition Pin Name Pin No IN FBIN 2 1 OUT1 OUT2 VDD GND FS0:1 6 8 7 3 4, 5 Pin Type I I O O P P I Pin Description Reference Input: The output signals are synchronized to this signal. Feedback Input: This input must be fed by one of the outputs (OUT...