DatasheetsPDF.com

K4S560432E-NCL75 Dataheets PDF



Part Number K4S560432E-NCL75
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description SDRAM 256Mb E-die
Datasheet K4S560432E-NCL75 DatasheetK4S560432E-NCL75 Datasheet (PDF)

SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 256Mb E-die SDRAM Specification 54pin sTSOP-II Revision 1.0 August. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) Revision History Revision 1.0 (August. 2003) - First release. CMOS SDRAM Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC .

  K4S560432E-NCL75   K4S560432E-NCL75


Document
SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 256Mb E-die SDRAM Specification 54pin sTSOP-II Revision 1.0 August. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) Revision History Revision 1.0 (August. 2003) - First release. CMOS SDRAM Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (8K Cycle) GENERAL DESCRIPTION The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. K4S560432E-NC(L)75 K4S560832E-NC(L)75 K4S561632E-NC(L)60/75 Orgainization 64M x 4 32M x 8 16M x 16 Max Freq. 133MHz 133MHz 166/133MHz Interface LVTTL LVTTL LVTTL Package 54pin sTSOP 54pin sTSOP 54pin sTSOP Organization 64Mx4 32Mx8 16Mx16 Row Address A0~A12 A0~A12 A0~A12 Column Address A0-A9, A11 A0-A9 A0-A8 Row & Column address configuration Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) Package Physical Dimension 54pin sTSOP(II)-300 #54 (1.00) #28 (∅ 2.00 Dp0~0.05 BTM) (1.00) #1 #27 (2-R 0.30) (2-R 0.15) (0.50) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY 14.40MAX (14.20) 14.00±0.10 (14°) 0.50TYP 0.50±0.05 [ 0.07 MAX ] 0.20 +0.075 -0.035 (14°) 0.665±0.05 0.210±0.05 0.05 MIN 1.00±0.05 7.6 1.20MAX (1.10) CMOS SDRAM Units : Millimeters (2-R 0.15) (2-R 0.30) (0.50) (0.80) (8.22) 9.22±0.20 (R0.25) (14°) (R0.25) 0.40~0.60 (14°) 0.125 +0.075 -0.035 (0.50) (0.80) 0.10 MAX 0.25TYP 0×~8× Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) FUNCTIONAL BLOCK DIAGRAM CMOS SDRAM I/O Control Data Input Register Address Register CLK ADD Row Buffer Refresh Counter Bank Select Row Decoder 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 Column Decoder Col. Buffer LCBR LRAS LCKE LRAS LCBR LWE LCAS Latency & Burst Length Programming Register LWCBR Timing Register Sense AMP Output Buffer LWE LDQM DQi LDQM CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM PIN CONFIGURATION (Top view) x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 x4 x8 x16 54 VSS VSS VSS 53 NC DQ7 DQ15 52 VSSQ VSSQ VSSQ 51 NC NC DQ14 50 DQ3 DQ6 DQ13 49 VDDQ VDDQ VDDQ 48 NC NC DQ12 47 NC DQ5 DQ11 46 VSSQ VSSQ VSSQ 54 PIN sTSOP(II) 45 NC NC DQ10 44 DQ2 DQ4 DQ9 43 VDDQ VDDQ VDDQ 300mil x 551mil 42 NC NC DQ8 (7.62mm x 14.00mm) 41 VSS VSS VSS (0.5 mm pin pitch) 40 NC NC NC 39 DQM DQM UDQM 38 CLK CLK CLK 37 CKE CKE CKE 36 A12 A12 A12 35 A11 A11 A11 34 A9 A9 A9 33 A8 A8 A8 32 A7 A7 A7 31 A6 A6 A6 30 A5 A5 A5 29 A4 A4 A4 28 VSS VSS VSS PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select CKE Clock enable A0 ~ A12 Address BA0 ~ BA1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM Data input/output mask DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU Data input/output Power supply/ground Data output power/ground No connection /reserved for future use Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address .


K4S560432E-NC75 K4S560432E-NCL75 K4S560832E-NC75


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)