Document
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
128Mb F-die SDRAM Specification
t4U.com54 TSOP-II with Pb-Free e(RoHS compliant)
w.DataSheRevision 1.2 ww August 2004
heet4U.com* Samsung Electronics reserves the right to change products or specification without notice. www.DataSRev. 1.2 August 2004
SDRAM 128Mb F-die (x4, x8, x16)
Revision History
Revision 1.0 (January, 2004) - First release.
Revision 1.1 (May, 2004) • Added Note 5. sentense of tRDL parameter.
Revision 1.2 (August, 2004) • Corrected typo.
CMOS SDRAM
Rev. 1.2 August 2004
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs
-. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K Cycle) • 54 TSOP(II) Pb-free Package • RoHS compliant
GENERAL DESCRIPTION
The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. K4S280432F-UC(L)75 K4S280832F-UC(L)75 K4S281632F-UC(L)60/75
Orgainization 32M x 4 16M x 8 8M x 16
Max Freq. 133MHz 133MHz 166MHz
Interface LVTTL LVTTL LVTTL
Package 54pin TSOP(II) 54pin TSOP(II) 54pin TSOP(II)
Organization 32Mx4 16Mx8 8Mx16
Row Address A0~A11 A0~A11 A0~A11
Column Address A0-A9, A11 A0-A9 A0-A8
Row & Column address configuration
Rev. 1.2 August 2004
SDRAM 128Mb F-die (x4, x8, x16)
Package Physical Dimension
#54 #28
CMOS SDRAM
00..02150 TYP
0~8°C
0.45~0.75 0.018~0.030
10.16 0.400
11.76±0.20 0.463±0.008
( 00..05200)
#1
0.10 0.004
MAX
(00..07218)
22.62 0.891
MAX
22.22 ± 0.10 0.875 ± 0.004
#27
0.125+-00..007355 0.005+-00..000031
0.21 ± 0.05 0.008 ± 0.002
1.00 ± 0.10 0.039 ± 0.004
1.20 0.047
MAX
0.30+-00..1005
0.012
+0.004 -0.002
0.80 0.0315
0.05 0.002
MIN
54Pin TSOP Package Dimension
Rev. 1.2 August 2004
SDRAM 128Mb F-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
Data Input Register
Address Register
CLK ADD
Row Buffer Refresh Counter
Bank Select
Row Decoder
8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16
Column Decoder
Col. Buffer
LCBR LRAS
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register LWCBR
Timing Register
Sense AMP
Output Buffer
LWE LDQM DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 August 2004
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
PIN CONFIGURATION (Top view)
x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS
CS BA0 BA1 A10/AP
A0 A1 A2 A3 VDD
x8 x4
VDD
VDD
DQ0 N.C
VDDQ VDDQ
N.C N.C
DQ1 DQ0
VSSQ VSSQ
N.C N.C
DQ2 N.C
VDDQ VDDQ
N.C N.C
DQ3 DQ1
VSSQ VSSQ
N.C N.C
VDD
VDD
N.C N.C
WE WE
CAS CAS
RAS RAS
CS CS
BA0 BA0
BA1 BA1
A10/AP A10/AP
A0 A0
A1 A1
A2 A2
A3 A3
VDD
VDD
PIN FUNCTION DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
x4 x8 x16
54 VSS VSS VSS
53 N.C
DQ7
DQ15
52 VSSQ
VSSQ
VSSQ
51 N.C N.C DQ14
50 DQ3
DQ6
DQ13
49 VDDQ
VDDQ
VDDQ
48 N.C N.C DQ12
47 N.C
DQ5
DQ11
46 VSSQ
VSSQ
VSSQ
45 N.C N.C DQ10
44 DQ2
DQ4
DQ9
43 VDDQ
VDDQ
VDDQ
42 N.C N.C DQ8
41 VSS VSS VSS
40 N.C/RFU N.C/RFU N.C/RFU
39 DQM DQM UDQM
38 CLK
CLK
CLK
37 CKE
CKE
CKE
36 N.C N.C N.C
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch)
Pin CLK
CS
Name System clock
Chip select
CKE
Clock enable
A0 ~ A11
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM
Data input/output mask
DQ0 ~ N VDD/VSS VDDQ/VSSQ
N.C/RFU
Data input/output
Power supply/ground
Data output power/ground
No connection /reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle pr.