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IS42S16160 Dataheets PDF



Part Number IS42S16160
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 16Meg x16 256-MBIT SYNCHRONOUS DRAM
Datasheet IS42S16160 DatasheetIS42S16160 Datasheet (PDF)

IS42S16160 16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S16160 Vdd Vddq 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 6.

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IS42S16160 16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S16160 Vdd Vddq 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Available in Industrial Temperature • Available in 54-pin TSOP-II and 54-ball TF-BGA • Available in Lead-free OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42S16160 4M x16x4 Banks 54-pin TSOPII 54-ball TF-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 6 7 10 10 166 143 100 100 5.4 5.4 8 8 -75E Unit – ns 7.5 ns – Mhz 133 Mhz – ns 5.5 ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev.  C 09/15/09 1 IS42S16160 DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled.  Precharge one bank while acc.


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