Toggle DDR1.0. TC58TEG6DCJTA00 Datasheet

TC58TEG6DCJTA00 DDR1.0. Datasheet pdf. Equivalent

Part TC58TEG6DCJTA00
Description NAND memory Toggle DDR1.0
Feature TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 TOSHIBA NAND memory Toggle DDR1.0 Technical Data Sheet Rev. 0..
Manufacture Toshiba
Datasheet
Download TC58TEG6DCJTA00 Datasheet



TC58TEG6DCJTA00
TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0
TOSHIBA
NAND memory
Toggle DDR1.0
Technical Data Sheet
Rev. 0.3
2012 – 04 – 10
TOSHIBA
Semiconductor & Storage Products
Memory Division
TC58TEG6DCJTA00 / TC58TEG6DCJTAI0
TH58TEG7DCJTA20 / TH58TEG7DCJTAK0
TH58TEG8DCJTA20 / TH58TEG8DCJTAK0
0
TENTATIVE 2012-04-10C



TC58TEG6DCJTA00
1. INTRODUCTION
TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0
1.1. General Description
Toggle DDR is a NAND interface for high performance applications which support data read and write operations
using bidirectional DQS.
Toggle DDR NAND has implemented ’Double Data Rate’ without a clock. It is compatible with functions and
command which have been supported in conventional type NAND(i.e. SDR NAND) while providing high data
transfer rate based on the high-speed Toggle DDR Interface and saving power with separated DQ voltage. For
applications that require high capacity and high performance NAND, Toggle DDR NAND is the most appropriate.
Toggle DDR1.0 NAND supports the interface speed of up to 100 MHz, which is faster than the data transfer rate
offered by SDR NAND. Toggle DDR NAND transfers data at high speed using DQS signal that behaves as a clock,
and DQS shall be used only when data is transferred for optimal power consumption.
This device supports both SDR interface and Toggle DDR interface. When starting, the device is activated in SDR
mode. The interface mode can be changed into Toggle DDR interface utilizing specific command issued by the Host.
1.2. Definitions and Abbreviations
SDR
Acronym for single data rate.
DDR
Acronym for double data rate.
Address
The address is comprised of a column address with 2 cycles and a row address with 3 cycles. The row address
identifies the page, block and LUN to be accessed. The column address identifies the byte within a page to access.
The least significant bit of the column address shall always be zero.
Column
The byte location within the page register.
Row
Refer to the block and page to be accessed.
Page
The smallest addressable unit for the Read and the Program operations.
Block
Consists of multiple pages and is the smallest addressable unit for the Erase operation.
Plane
The unit that consists of a number of blocks. There are one or more Planes per LUN.
Page register
Register used to transfer data to and from the Flash Array.
Cache register
Register used to transfer data to and from the Host.
Defect area
The defect area is where factory defects are marked by the manufacturer. Refer to the section 3.2
Device
The packaged NAND unit. A device may contain more than a target.
TC58TEG6DCJTA00 / TC58TEG6DCJTAI0
TH58TEG7DCJTA20 / TH58TEG7DCJTAK0
TH58TEG8DCJTA20 / TH58TEG8DCJTAK0
1
TENTATIVE 2012-04-10C





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)