HYB25DC256163CE-6

HYB25DC256163CE-4 HYB25DC256163CE-5 HYB25DC256163CE-6 256-Mbit Double-Data-Rate SGRAM Green Product January 2007 Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB25DC256163CE-4, HYB25DC256163CE-5, HYB25DC256163CE-6 Revision History: 2007-01, Rev. 1.1 Page Subjects (major changes since last revision) All Adapted internet edition All Added new speedsort -4 Previous Revision: 2007-01, Rev. 1.0 HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-SR4U-HULB 2 Internet Data Sheet 1 Overview HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM This chapter lists all main features of the product family HYB25DC256163CE and the ordering information. 1.1 Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; ...