High-Performance CPLD. XC9500XL Datasheet

XC9500XL CPLD. Datasheet pdf. Equivalent

Part XC9500XL
Description High-Performance CPLD
Feature k 0 R XC9500XL High-Performance CPLD Family Data Sheet DS054 (v2.5) May 22, 2009 0 0 Product Speci.
Manufacture Xilinx
Datasheet
Download XC9500XL Datasheet

k 0 R XC9500XL High-Performance CPLD Family Data Sheet DS05 XC9500XL Datasheet
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XC9500XL
k
0
R XC9500XL High-Performance CPLD
Family Data Sheet
DS054 (v2.5) May 22, 2009
0 0 Product Specification
Features
• Optimized for high-performance 3.3V systems
- 5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
- Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
- Pb-free available for all packages
- Lower power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Supports hot-plugging capability
- Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable
gates
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention
• Pin-compatible with 5V core XC9500 family in common
package footprints
Table 1: XC9500XL Device Family
XC9536XL
XC9572XL
XC95144XL
XC95288XL
Macrocells
Usable Gates
36 72 144 288
800
1,600
3,200
6,400
Registers
TPD (ns)
TSU (ns)
TCO (ns)
fSYSTEM (MHz)
36 72 144 288
5556
3.7 3.7 3.7 4.0
3.5 3.5 3.5 3.8
178 178 178 208
© 1998–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
1



XC9500XL
R XC9500XL High-Performance CPLD Family Data Sheet
Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated JTAG pins)
Package(1)
XC9536XL
XC9572XL
XC95144XL
PC44
34 34
-
PCG44
34 34
VQ44
34 34
-
VQG44
34 34
CS48
36 38
-
CSG48
36 38
VQ64
36 52
-
VQG64
36 52
TQ100
- 72 81
TQG100
72 81
CS144
- - 117
CSG144
117
TQ144
- - 117
TQG144
117
PQ208
---
PQG208
BG256
---
BGG256
FG256
---
FGG256
CS280
---
CSG280
Notes:
1. The letter "G" as the third character indicates a Pb-free package.
XC95288XL
-
-
-
-
-
-
117
117
168
168
192
192
192
192
192
192
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
2





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